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6. 0 --> S flag
7. (TBR + vector offset of the accepted interrupt request) --> PC
At the end of the interrupt sequence, the CPU detects a new EIT before executing the first
instruction of the handler. If there is an acceptable EIT at this time, the CPU proceeds with the
EIT processing sequence.
I Operation for INT instruction
The INT #u8 instruction operates as follows:
Control branches to the interrupt handler of the vector indicated by u8.
Each item in parentheses in 1. to 7. below shows the address indicated by the register.
❍ Operation
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC + 2 --> (SSP)
5. 0 --> I flag
6. 0 --> S flag
7. (TBR + 3FCH - 4 x u8) --> PC
I Operation for INTE instruction
The INTE instruction operates as follows:
Control branches to the interrupt handler of the vector with vector number 9.
Each item in parentheses in 1. to 7. below shows the address indicated by the register.
❍ Operation
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC + 2 --> (SSP)
5. 00100 --> ILM
6. 0 --> S flag
7. (TBR + 3D8H) --> PC
Do not use the INTE instruction within another INTE instruction or in the step trace trap
processing routine.
No EIT is generated by INTE during step execution.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
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