Basic Write Cycle - Fujitsu MB91150 Series Hardware Manual

CHAPTER 4 BUS INTERFACE
4.5.2

Basic Write Cycle

This section describes the operations of the basic write cycle.
I Basic write cycle timing chart
Figure 4.5-2 "Example of a timing chart of basic write cycle" shows an example of basic write
cycle timing under the following conditions:
• Bus width: 8 bits
• Access type: in words
• Access to CS0 area
Note:
This model does not use CS4 and CS5 outputs.
CLK
A23-00
D31-24
D23-16
RD
WR0
WR1
(CS0)
(CS1)
(CS2)
(CS3)
(DACK0)
(DEOP0)
[Operation]
• A23 to A00 (address 23 to address 00) output the address of the leading byte for word, half
word, or byte access during a write cycle starting from the beginning of a bus cycle (BA1). In
the above example, because a word is accessed in a width of eight bits, the address of the
leading byte of the word (the lower bits of the address indicate 0) is output. Then, the
address for the leading byte address plus 1 (1), the address of the leading byte address plus
2 (2), and the address for the leading byte address plus 3 (3) are output in sequence.
• D31 to D16 (data 31 to data 16) indicate write data for the external memory and I/O. In a
write cycle, write data is output starting from the beginning of a bus cycle (BA1) and set to
High-Z at the end of the bus cycle (end of the BA2). In the above example, write data is
output to D31 to D24 because of the data bus has a width of 8 bits.
• The RD is negated during a write cycle.
• WR0 and WR1 are write strobe signals for the external bus data. They are asserted when
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Figure 4.5-2 Example of a timing chart of basic write cycle
BA1 BA2
#0
#0
Byte access when
Byte access when
the lower two bits the lower two bits
of the address of the address
indicate 0 indicate 1
BA1 BA2 BA1 BA2
#1 #2
#1 #2
Byte access when
the lower two bits
of the address
indicate 2
BA1 BA2
#3
#3
Byte access when
the lower two bits
of the address
indicate 3