Fujitsu MB91150 Series Hardware Manual page 284

CHAPTER 12 INTERRUPT CONTROLLER
Table 12.4-1 Relationship between interrupt sources, interrupt numbers, and interrupt
levels (Continued)
Interrupt source
UART3 (Sending completed)
DMAC (Exit and error)
Reload timer 0
Reload timer 1
Reload timer 2
Reload timer 3
A/D (Sequential type)
PPG0
PPG1
PPG2
PPG3
PPG4/5
U/D counter 0
U/D counter 1
ICU0 (Fetch)
ICU1 (Fetch)
ICU2 (Fetch)
ICU3 (Fetch)
OCU0 (Coincidence)
OCU0 (Coincidence)
OCU1 (Coincidence)
OCU2 (Coincidence)
OCU3 (Coincidence)
OCU4/5 (Coincidence)
OCU6/7 (Coincidence)
16-bit free running timer
Delayed interrupt source bit
I Releasing interrupt factors
The interrupt routine has restrictions on the relationship between an instruction for releasing
interrupt factors and the RETI instruction.
For details, see Chapter 3 "MEMORY SPACE, CPU and CONTROL UNIT".
268
Interrupt number
Decimal Hexadecimal
34 22
36 24
37 25
38 26
39 27
40 28
42 2A
43 2B
44 2C
45 2D
46 2E
47 2F
49 31
50 32
51 33
52 34
53 35
54 36
55 37
56 38
57 39
58 3A
59 3B
60 3C
60 3C
62 3E
63 3F
Interrupt Offset
level
ICR18 374
H
ICR20 36C
H
ICR21 368
H
ICR22 364
H
ICR23 360
H
ICR24 35C
H
ICR26 354
H
ICR27 350
H
ICR28 34C
H
ICR29 348
H
ICR30 344
H
ICR31 340
H
ICR33 338
H
ICR34 334
H
ICR35 330
H
ICR36 32C
H
ICR37 328
H
ICR38 324
H
ICR39 320
H
ICR40 31C
H
ICR41 318
H
ICR42 314
H
ICR43 310
H
ICR44 30C
H
ICR44 30C
H
ICR46 304
H
ICR47 300
H
TBR default
address
000FFF74
H
000FFF6C
H
000FFF68
H
000FFF64
H
000FFF60
H
000FFF5C
H
000FFF54
H
000FFF50
H
000FFF4C
H
000FFF48
H
000FFF44
H
000FFF40
H
000FFF38
H
000FFF34
H
000FFF30
H
000FFF2C
H
000FFF28
H
000FFF24
H
000FFF20
H
000FFF1C
H
000FFF18
H
000FFF14
H
000FFF10
H
000FFF0C
H
000FFF0C
H
000FFF04
H
000FFF00
H