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CHAPTER 1 OVERVIEW OF THE MB91150
I Block diagram for MB91154
Figure 1.2-2 "Block diagram (MB91154)" is a block diagram for the MB91154.
MD0
MD1
MD2
RST
P37/D31(IO)
P30/D24
DATA
P27/D23
P20/D16
P67/A23(O)
P60/A16
P57/A15
Address
P50/A8
P47/A7
P40/A0
P86/CLK(O)
P85/WR1(O)
Bus
P84/WR0
Control
P83/RD(O)
P82/BRQ(I)
P81/BGRNT(O)
P80/RDY(I)
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
DMAC
PL3/DREQ1
PL2/DEOP0(O)
PL1/DACK0(O)
PL0/DREQ0(I)
X0 (I)
Clock
X1 (I)
A/D
PD7/INT15/ATG(I)
DMAC
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
Up/Down
PD2/INT10/AIN1
Counter
PD1/INT9/BIN0(I)
PD0/INT8/AIN0(I)
External
PC7/INT7/CS3
Interrupt
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0(I)
6
Figure 1.2-2 Block diagram (MB91154)
M
O
FR30 CPU Core
D
E
D-Bus
I-Bus
(4)
P
O
R
T
3
/
2
(16)
P
O
R
T
6
/
5
/
4
D-Bus
I-Bus
(24)
C-Bus
P
O
R
External
T
Bus CTL
8
(7)
RAM
2KB
P
O
R
ROM
T
384KB
L
(8)
OSC
Clock
(2)
Control
P
Interrupt
O
Controller
R
T
D
(8)
8bit
Up/Down
Counter
2ch
P
O
R
T
External
2
I
C Interface
C
Interrupt
1ch
16ch
(8)
OSC
Calendar
(2)
Data RAM
20KB
P
O
R
T
E
DMAC 8ch
(8)
Bit Search
P
O
R
T
D-Bus
R-Bus
G
(6)
P
O
R
UART 4ch
T
UTIMER 4ch
H
(6)
16bit
P
Reload Timer
O
R
4ch
T
16bit
I
(6)
Free RUN Timer
1ch
P
O
16bit PPG
R
T
6ch
J
(2)
16bit
Input Capture
P
O
4ch
R
T
16bit
K
Output Compare
(8)
8ch
10bit 8input
P
A/D converter
O
R
T
F
(5)
8bit 3output
D/A converter
D
A
2
I
C Interface
(3)
1ch
X0A
Clock
X1A
PE7/OC7
PE6/OC6
PE5/OC5
PE4/OC4
Output
PE3/OC3
Compare
PE2/OC2
PE1/OC1
PE0/OC0
PG5/PPG5
PG4/PPG4
PG3/PPG3
PPG
PG2/PPG2
PG1/PPG1
PG0/PPG0
PH0/SIN0
PH1/SOT0
PH2/SCK0/T00
PH3/SIN1
PH4/SOT1
PH5/SCK1/T01
UART
PI0/SIN2
TOX:
Reload
PI1/SOT2
Timer
PI2/SCK2/T02
PI3/SIN3
PI4/SOT3
PI5/SCK3/T03
PJ0/SCL
2
I
C
PJ1/SDA
PK0/AN0
PK1/AN1
PK2/AN2
PK3/AN3
A/D
PK4/AN4
PK5/AN5
PK6/AN6
PK7/AN7
PF4
PF3/IN3
PF2/IN2
Input
PF1/IN1
Capture
PF0/IN0
DA2
DA1
DA0
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