Fujitsu MB91150 Series Hardware Manual page 506

INDEX
descriptor start word............................................. 370
descriptor, second word in ................................... 372
descriptor, third word in........................................ 372
detect error, failure to ........................................... 464
detection result register (BSRR)........................... 396
direct addressing area............................................ 30
direct addressing instruction ................................ 485
DLYI bit of DICR...................................................258
DMA controller, block diagram of .........................363
DMA controller, feature of .................................... 362
DMA controller, register of.................................... 364
DMA request suppression register (PDRR) ........... 76
DMA transfer request, note on using resource
interrupt request as .................................... 382
DMAC control status register (DACSR) ............... 366
DMAC internal register, transfer operation to....... 383
DMAC parameter descriptor pointer (DPDP) ....... 365
DMAC pin control register (DATCR) .................... 368
double type and long-double type, using ............. 462
timer mode ........................................................... 178
DREC signal sense mode .................................... 375
E
edge mode, note on ............................................. 380
EIT source.............................................................. 53
EIT source acceptance priority............................... 58
EIT vector table ...................................................... 56
EIT, note on............................................................ 53
EIT, return from ...................................................... 53
emulator debugger and monitor debugger ........... 465
enable interrupt register (ENIRn) .........................250
entire PPG timer, block diagram of ...................... 201
EPCR0 ................................................................. 110
EPCR1 ................................................................. 112
external access in big-endian and little-endian mode,
comparison of ............................................114
external bus access (in big-endian mode)............118
external bus operation, program example for....... 147
external bus operation, specification example of
program for ................................................ 146
external bus request............................................. 131
external clock ......................................................... 26
external clock, baud rate based on ...................... 333
external interrupt control block, block diagram of. 248
external interrupt operation .................................. 253
external interrupt register, list of........................... 249
external interrupt request level ............................. 254
external interrupt request register (EIRRn) .......... 251
external interrupt, setting procedure for ............... 253
490
external level register (ELVR) .............................. 252
external pin control register 0............................... 110
external pin control register 1............................... 112
external reset input ................................................ 26
external wait cycle, timing chart of ....................... 142
F
flash memory in read/reset status, placing .......... 433
flash memory write, procedure for ....................... 434
flash memory, block diagram of ........................... 415
flash memory, note on writing data to .................. 434
flash memory, overview of ................................... 414
flash memory, writing data to ............................... 434
FPT-144P-M08, package dimension of (MB91F155A,
MB91155 and MB91154)............................... 8
FR series instruction list....................................... 470
FR-CPU programming mode (16 bits, read/write) 421
FR-CPU ROM mode (32 bits, read only) ............. 421
G
GCN, activating multiple channel with ................. 222
gear control block, block diagram of ...................... 80
gear control register (GCR).................................... 73
gear function, setting of.......................................... 81
general control register 1 (GCN1)........................ 212
general control register 2 (GCN2)........................ 215
general-purpose register........................................ 37
H
half word access (external access in big-endian and
little-endian mode) ..................................... 127
hardware configuration ........................................ 271
hardware sequence flag....................................... 427
higher bit of A/D control status register (ADCS1) 282
higher-priority interrupt, suppression of DMA transfer
upon generation of..................................... 382
hold request cancellation request, level that can be
set for......................................................... 270
hold-request cancellation request level set register
(HRCL)....................................................... 266
hold-request cancellation-request must be issued,
criteria for determining whether ................. 270
hold-request cancellation-request sequence ....... 272
hour data register (CA3) ...................................... 408
HRCL register ...................................................... 382
I
I/O circuit type ........................................................ 20
I/O map ................................................................ 441