Fujitsu MB91150 Series Hardware Manual page 500

APPENDIX
I 32-bit delayed branch macroinstructions
Table E-19 32-bit delayed branch macroinstructions
.Mnemonic
*CALL32:D label32,Ri
*BRA32:D label32,Ri
*BEQ32:D label32,Ri
*BNE32:D label32,Ri
*BC32:D label32,Ri
*BNC32:D label32,Ri
*BN32:D label32,Ri
*BP32:D label32,Ri
*BV32:D label32,Ri
*BNV32:D label32,Ri
*BLT32:D label32,Ri
*BGE32:D label32,Ri
*BLE32:D label32,Ri
*BGT32:D label32,Ri
*BLS32:D label32,Ri
*BHI32:D label32,Ri
[Reference 1] CALL32:D
1) When label32-PC-2 is -0x800 to +0x7fe, the instruction is generated as follows:
CALL:D label12
2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:32 #label32,Ri
CALL:D @Ri
[Reference 2] BRA32:D
1) When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
BRA:D label9
2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
LDI:32 #label32,Ri
JMP:D @Ri
[Reference 3] Bcc32:D
1) When label32-PC-2 is -0x100 to +0xfe, the instruction is generated as follows:
Bcc:D label9
2) When label32-PC-2 exceeds the range in condition 1) or contains an external reference symbol, the
instruction is generated as follows:
Bxcc false xcc is a condition against cc.
LDI:32 #label32,Ri
JMP:D @Ri
false:
484
Operation
Address of the next instruction + 2
--> RP
label32 --> PC
label32 --> PC
if(Z==1) then label32 -->PC
s/Z==0
s/C==1
s/C==0
s/N==1
s/N==0
s/V==1
s/V==0
s/V xor N==1
s/V xor N==0
s/(V xor N) or Z==1
s/(V xor N) or Z==0
s/C or Z==1
s/C or Z==0
Remarks
Ri: Temporary register (See Reference 1.)
Ri: Temporary register (See Reference 2.)
Ri: Temporary register (See Reference 3.)