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Fujitsu MB95630H Series Hardware Manual

8-bit microcontroller new 8fx.
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FUJITSU SEMICONDUCTOR
MN702-00009-1v0-E
CONTROLLER MANUAL
8-BIT MICROCONTROLLER
New 8FX
MB95630H Series
HARDWARE MANUAL

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   Summary of Contents for Fujitsu MB95630H Series

  • Page 1

    FUJITSU SEMICONDUCTOR MN702-00009-1v0-E CONTROLLER MANUAL 8-BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL...

  • Page 3

    8-BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL For the information for microcontroller supports, see the following website. http://edevice.fujitsu.com/micom/en-support/ FUJITSU SEMICONDUCTOR LIMITED...

  • Page 5: Sample Programs

    ■ The Purpose and Intended Readership of This Manual Thank you very much for your continued special support for Fujitsu Semiconductor products. The MB95630H Series is a line of products developed as general-purpose products in the New 8FX family of proprietary 8-bit single-chip microcontrollers applicable as application-specific integrated circuits (ASICs).

  • Page 6: How To Use This Manual

    How to Use This Manual ■ Finding a Function The following methods can be used to search for details of a function in this manual: • Searching from CONTENTS CONTENTS lists the contents in this manual in the order of description. •...

  • Page 7

    (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that FUJITSU SEMICONDUCTOR will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products.

  • Page 9: Table Of Contents

    CONTENTS CHAPTER 1 MEMORY ACCESS MODE .............. 1 Memory Access Mode ......................2 CHAPTER 2 CPU ....................3 Dedicated Registers ......................4 2.1.1 Register Bank Pointer (RP) .................... 6 2.1.2 Direct Bank Pointer (DP) ....................7 2.1.3 Condition Code Register (CCR) ..................9 General-purpose Register ....................

  • Page 10: Table Of Contents

    5.1.3 Nested Interrupts ......................77 5.1.4 Interrupt Processing Time .................... 78 5.1.5 Stack Operation During Interrupt Processing ............... 79 5.1.6 Interrupt Processing Stack Area ................... 80 CHAPTER 6 I/O PORT ..................81 Overview ..........................82 Configuration and Operations .................... 83 CHAPTER 7 TIME-BASE TIMER ................

  • Page 11: Table Of Contents

    11.3 Channel ........................... 141 11.4 Pins ..........................142 11.5 Interrupts ......................... 143 11.6 Operation of Interval Timer Function (One-shot Mode) ........... 144 11.7 Operation of Interval Timer Function (Continuous Mode) ..........146 11.8 Operation of Interval Timer Function (Free-run Mode) ............ 148 11.9 Operation of PWM Timer Function (Fixed-cycle mode) ..........

  • Page 12: Table Of Contents

    14.6.1 Operations in Asynchronous Mode (Operating Mode 0, 1) ........223 14.6.2 Operations in Synchronous Mode (Operating Mode 2) ..........227 14.6.3 Operations of LIN function (Operating Mode 3) ............231 14.6.4 Serial Pin Direct Access ..................... 234 14.6.5 Bidirectional Communication Function (Normal Mode) ..........235 14.6.6 Master/Slave Mode Communication Function (Multiprocessor Mode) .......

  • Page 13

    18.2 Configuration ........................307 18.3 Channel ........................... 309 18.4 Pins ..........................310 18.5 Interrupt ........................... 311 18.6 Operations and Setting Procedure Example ..............312 18.6.1 8-bit PPG Independent Mode ..................313 18.6.2 8-bit Prescaler + 8-bit PPG Mode ................315 18.6.3 16-bit PPG Mode ......................

  • Page 14: Table Of Contents

    CHAPTER 21 MULTI-PULSE GENERATOR ............377 21.1 Overview .......................... 378 21.2 Block Diagram ......................... 381 21.3 Pins ..........................389 21.4 Interrupts ......................... 390 21.5 Operations ........................392 21.5.1 Operation of Position Detection .................. 394 21.5.2 Operation of Data Write Control Unit ................396 21.5.3 Operation of 16-bit MPG Output Data Buffer Register (Upper/Lower) (OPDBRHx/OPDBRLx) ....................

  • Page 15: Table Of Contents

    22.6.2 Operations in Operation Mode 1 ................470 22.7 Registers ......................... 476 22.7.1 UART/SIO Serial Mode Control Register 1 (SMC1n) ..........477 22.7.2 UART/SIO Serial Mode Control Register 2 (SMC2n) ..........479 22.7.3 UART/SIO Serial Status and Data Register (SSRn) ..........481 22.7.4 UART/SIO Serial Input Data Register (RDRn) ............

  • Page 16: Table Of Contents

    25.5.5 Suspending Sector Erase from Flash Memory ............552 25.5.6 Resuming Sector Erase of Flash Memory ..............553 25.5.7 Unlock Bypass Program ..................... 554 25.6 Operations ........................555 25.7 Flash Security ........................557 25.8 Registers ......................... 558 25.8.1 Flash Memory Status Register 2 (FSR2) ..............559 25.8.2 Flash Memory Status Register (FSR) .................

  • Page 17

    Major revisions in this edition A change on a page is indicated by a vertical line drawn on the left of that page. Page Revisions (For details, see their respective pages.) How to Use This Manual Added the following section. ■...

  • Page 18

    Page Revisions (For details, see their respective pages.) 6.2 Configuration and Operations of Revised the following statement. I/O Port Set the bit in the DDRx register corresponding to the analog ■ Operations of I/O Port input pin to "0" and the bit corresponding to that pin in the ●...

  • Page 19

    Page Revisions (For details, see their respective pages.) CHAPTER 22 UART/SIO Corrected the following register abbreviation in the 22.7 UART/SIO Serial Status and respective details of the PER bit, the OVE bit and the FER Data Register (SSRn) bit. ■ Register Functions SMR2n →...

  • Page 21: Chapter 1 Memory Access Mode

    CHAPTER 1 MEMORY ACCESS MODE This chapter describes the memory access mode. Memory Access Mode MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 22: Memory Access Mode

    CHAPTER 1 MEMORY ACCESS MODE MB95630H Series 1.1 Memory Access Mode Memory Access Mode The MB95630H Series supports only one memory access mode: single-chip mode. ■ Single-chip Mode In single-chip mode, only the internal RAM and the Flash memory are used, and no external bus access is executed.

  • Page 23: Chapter 2 Cpu

    CHAPTER 2 This chapter describes the functions and operations of the CPU. Dedicated Registers General-purpose Register Placement of 16-bit Data in Memory MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 24: Dedicated Registers

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers Dedicated Registers The CPU has dedicated registers: a program counter (PC), two registers for arithmetic operations (A and T), three address pointers (IX, EP, and SP), and the program status (PS) register. Each of the registers is 16 bits long. The PS register consists of the register bank pointer (RP), direct bank pointer (DP), and condition code register (CCR).

  • Page 25

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers ● Temporary accumulator (T) The temporary accumulator is an auxiliary 16-bit register for arithmetic operation. It is used to perform arithmetic operations with the data in the accumulator (A). The data in the temporary accumulator is handled as word data for word-length (16-bit) operations with the accumulator (A) and as byte data for byte-length (8-bit) operations.

  • Page 26: Register Bank Pointer (rp), Register Bank Pointer (rp)

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers 2.1.1 Register Bank Pointer (RP) The register bank pointer (RP) in bit15 to bit11 of the program status (PS) register contains the address of the general-purpose register bank that is currently in use and is translated into a real address when general-purpose register addressing is used.

  • Page 27: Direct Bank Pointer (dp), Direct Bank Pointer (dp)

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers 2.1.2 Direct Bank Pointer (DP) The direct bank pointer (DP) in bit10 to bit8 of the program status (PS) register specifies the area to be accessed by direct addressing. ■ Configuration of Direct Bank Pointer (DP) Figure 2.1-4 shows the configuration of the direct bank pointer.

  • Page 28

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers Table 2.1-2 Direct Address Instruction List Applicable instructions CLRB dir:bit SETB dir:bit BBC dir:bit,rel BBS dir:bit,rel MOV A,dir CMP A,dir ADDC A,dir SUBC A,dir MOV dir,A XOR A,dir AND A,dir OR A,dir...

  • Page 29: Condition Code Register (ccr), Condition Code Register (ccr)

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers 2.1.3 Condition Code Register (CCR) The condition code register (CCR) in the lower eight bits of the program status (PS) register consists of the bits (H, N, Z, V, and C) containing information about the arithmetic result or transfer data and the bits (I, IL1, and IL0) used to control the acceptance of interrupt requests.

  • Page 30

    CHAPTER 2 CPU MB95630H Series 2.1 Dedicated Registers ● Carry flag (C) This flag is set to "1" when a carry from bit7 or a borrow to bit7 occurs due to the result of an operation. Otherwise, the flag is set to "0". When a shift instruction is executed, the flag is set to the shift-out value.

  • Page 31: General-purpose Register

    CHAPTER 2 CPU MB95630H Series 2.2 General-purpose Register General-purpose Register The general-purpose registers are a memory block in which each bank consists of eight 8-bit registers. Up to 32 register banks can be used in total. The register bank pointer (RP) is used to specify a register bank.

  • Page 32

    CHAPTER 2 CPU MB95630H Series 2.2 General-purpose Register ■ Features of General-purpose Registers The general-purpose register has the following features. • High-speed access to RAM with short instructions (general-purpose register addressing). • Grouping registers into a block of register banks facilitates data protection and division of registers in terms of functions.

  • Page 33: Placement Of 16-bit Data In Memory

    CHAPTER 2 CPU MB95630H Series 2.3 Placement of 16-bit Data in Memory Placement of 16-bit Data in Memory This section describes how 16-bit data is stored in memory. ■ Placement of 16-bit Data in Memory ● State of 16-bit data stored in RAM When 16-bit data is written to memory, the upper byte of the data is stored at a smaller address and the lower byte is stored at the next address.

  • Page 34

    CHAPTER 2 CPU MB95630H Series 2.3 Placement of 16-bit Data in Memory FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 35: Clock Controller

    Overview Oscillation Stabilization Wait Time Registers Clock Modes Operations in Low Power Consumption Mode (Standby Mode) Clock Oscillator Circuit Overview of Prescaler Configuration of Prescaler Operation of Prescaler 3.10 Notes on Using Prescaler MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 36: Overview

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview Overview The New 8FX family has a built-in clock controller that optimizes its power consumption. It supports both of the external main clock and the external subclock. The clock controller enables/disables clock oscillation, enables/disables the supply of clock signals to the internal circuit, selects the clock source, and controls the internal CR oscillator and frequency divider circuits.

  • Page 37

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview ■ Block Diagram of Clock Controller Figure 3.1-1 is the block diagram of the clock controller. Figure 3.1-1 Block Diagram of Clock Controller Standby control register 2 (STBC2) DSTBYX To Flash memory...

  • Page 38

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview ■ Configuration of Clock Controller ● Main clock oscillator circuit This block is the oscillator circuit for the main clock. ● Subclock oscillator circuit This block is the oscillator circuit for the subclock.

  • Page 39

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview ● System clock control register 2 (SYCC2) This register is used to enable/disable the oscillations of the main clock, main CR clock, subclock, and sub-CR clock, and to display the ready signals of main clock oscillation, subclock oscillation, sub-CR oscillation and main CR oscillation.

  • Page 40: Clock Modes

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview ■ Clock Modes There are five clock modes: • Main clock mode • Main CR clock mode • Main CR PLL clock mode • Subclock mode • Sub-CR clock mode. Table 3.1-1 shows the relationships between the clock modes and the machine clock (operating clock for the CPU and peripheral functions).

  • Page 41: Standby Mode

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview ■ Standby Mode The clock controller selects whether to enable or disable clock oscillation and clock supply to the internal circuitry according to the standby mode selected. With the exception of time-base timer mode and watch mode, the standby mode can be set independently of the clock mode.

  • Page 42

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview ■ Combinations of Clock Mode and Standby Mode Table 3.1-3 and Table 3.1-4 list the combinations of clock mode and standby mode, and the respective operating states of different internal circuits with different combinations of clock mode and standby mode.

  • Page 43

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.1 Overview Table 3.1-4 Combinations of Standby Mode and Clock Mode and Internal Operating States (2) Time-base timer Watch Stop Main CR Main CR Function Main clock clock mode/ Subclock Sub-CR Main clock clock mode/...

  • Page 44: Oscillation Stabilization Wait Time

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.2 Oscillation Stabilization Wait Time Oscillation Stabilization Wait Time The oscillation stabilization wait time is the time after the oscillator circuit stops oscillation until the oscillator resumes its stable oscillation at its natural frequency. The clock controller obtains the oscillation stabilization wait time after the start of oscillation by counting a specific number of oscillation clock cycles.

  • Page 45

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.2 Oscillation Stabilization Wait Time ■ PLL Clock Oscillation Stabilization Wait Time As with the oscillation stabilization wait time of the oscillator, when a request for state transition from PLL oscillation stopped state to oscillation start is generated due to an interrupt...

  • Page 46

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.2 Oscillation Stabilization Wait Time ■ Order of Priority for Oscillation Stabilization Wait Times When multiple clocks are enabled simultaneously, the clock controller counts the respective oscillation stabilization wait times of clocks according to a designated order of priority. Below are the respective orders of priority for counting different oscillation stabilization wait times in different clock modes.

  • Page 47: Registers

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers Registers This section provides details of registers of the clock controller. Table 3.3-1 List of Clock Controller Registers Register Register name Reference abbreviation SYCC System clock control register 3.3.1 PLLC PLL control register 3.3.2...

  • Page 48: System Clock Control Register (sycc), System Clock Control Register (sycc)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers 3.3.1 System Clock Control Register (SYCC) The system clock control register (SYCC) selects a machine clock divide ratio and a clock mode, and indicates the current clock mode. ■ Register Configuration Field...

  • Page 49: Pll Control Register (pllc), Pll Control Register (pllc)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers 3.3.2 PLL Control Register (PLLC) The PLL control register (PLLC) controls the main CR PLL clock multiplier settings. ■ Register Configuration Field MPEN MPMC1 MPMC0 MPRDY — — — — Attribute —...

  • Page 50: Oscillation Stabilization Wait Time Setting Register (watr)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers 3.3.3 Oscillation Stabilization Wait Time Setting Register (WATR) This register selects oscillation stabilization wait times. ■ Register Configuration Field SWT3 SWT2 SWT1 SWT0 MWT3 MWT2 MWT1 MWT0 Attribute Initial value ■ Register Functions [bit7:4] SWT[3:0]: Subclock oscillation stabilization wait time select bits These bits set the subclock oscillation stabilization wait time.

  • Page 51

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers [bit3:0] MWT[3:0]: Main clock oscillation stabilization wait time select bits These bits set the main clock oscillation stabilization wait time. Details bit3:0 Main clock (F ) = 4 MHz No. of cycles Writing "1111"...

  • Page 52: Standby Control Register (stbc), Standby Control Register (stbc)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers 3.3.4 Standby Control Register (STBC) The standby control register (STBC) controls transition from the RUN state to sleep mode, stop mode, time-base timer mode, or watch mode, sets the pin state in stop mode, time-base timer mode, and watch mode, and controls the generation of software resets.

  • Page 53

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers [bit4] SRST: Software reset bit This bit sets the software reset. The read value of this bit is always "0". bit4 Details Writing "0" Has no effect on operation. Writing "1" Generates a 3-machine clock reset signal.

  • Page 54: System Clock Control Register 2 (sycc2), System Clock Control Register 2 (sycc)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers 3.3.5 System Clock Control Register 2 (SYCC2) The system clock control register 2 (SYCC2) indicates the respective stabilization conditions of main clock oscillation, subclock oscillation, main CR clock oscillation and sub-CR clock oscillation, and controls main clock oscillation, subclock oscillation, main CR clock oscillation and sub-CR clock oscillation.

  • Page 55

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers [bit3] SOSCE: Subclock oscillation enable bit This bit enables or disables the subclock oscillation. When SCS[2:0] are set to "0b000", this bit will be automatically set to "1". When SCS[2:0] or SCM[2:0] are set to "0b000", writing "0" to this is has no effect on operation.

  • Page 56: Standby Control Register 2 (stbc2), Standby Control Register 2 (stbc)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.3 Registers 3.3.6 Standby Control Register 2 (STBC2) The standby control register 2 (STBC2) controls the deep standby mode. ■ Register Configuration Field — — — — — — — DSTBYX Attribute — —...

  • Page 57: Clock Modes

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.4 Clock Modes Clock Modes There are five clock modes: main clock mode, subclock mode, main CR clock mode, main CR PLL clock mode, and sub-CR clock mode. Mode switching occurs according to the settings in the system clock control register (SYCC).

  • Page 58

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.4 Clock Modes ■ Clock Mode State Transition Diagram There are five clock modes: main clock mode, subclock mode, main CR clock mode, main CR PLL clock mode and sub-CR clock mode. The device can switch between these modes according to the settings in the system clock control register (SYCC).

  • Page 59

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.4 Clock Modes Table 3.4-1 Clock Mode State Transition Table (1 / 2) Current Next State Description State After a reset, the device waits for the main CR clock oscillation stabilization wait time and the sub-CR clock oscillation stabilization wait time to elapse and transits to main CR clock mode.

  • Page 60

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.4 Clock Modes Table 3.4-1 Clock Mode State Transition Table (2 / 2) Current Next State Description State When the clock mode select bits in the system clock control register (SYCC:SCS[2:0]) are set to "0b110", the device transits to main CR clock mode after waiting for the Main CR clock/ main CR clock oscillation stabilization wait time.

  • Page 61: Operations In Low Power Consumption Mode (standby Mode)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) Operations in Low Power Consumption Mode (Standby Mode) There are four standby modes: sleep mode, stop mode, time-base timer mode and watch mode. ■ Overview of Transiting to and Returning from Standby Mode There are four standby modes: sleep mode, stop mode, time-base timer mode, and watch mode.

  • Page 62: Notes On Using Standby Mode

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) 3.5.1 Notes on Using Standby Mode Even if the standby control register (STBC) sets standby mode, transition to standby mode does not occur when an interrupt request has been generated from a peripheral resource.

  • Page 63

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) ■ In every standby mode, the following two operating modes can be selected. 1. Deep standby mode (STBC2:DSTBYX = 0) In standby mode, the power consumption in deep standby mode is lower than that in normal standby mode.

  • Page 64

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) ■ Standby Mode State Transition Diagram (with Deep Standby Mode Disabled) Figure 3.5-1 shows a standby mode state transition diagram (with deep standby mode disabled).

  • Page 65

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) Table 3.5-1 Table of State Transition with Deep Standby Mode Disabled (Transition to and from Standby Mode) (2 / 2) State transition Description The device transits to watch mode when "1" is written to the watch bit in the standby control register (STBC:TMD) in subclock mode or sub-CR clock mode.

  • Page 66: Operations In Low Power Consumption Mode (standby Mode)

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) ■ Standby Mode State Transition Diagram (with Deep Standby Mode Enabled) Figure 3.5-2 shows a standby mode state transition diagram (with deep standby mode enabled).

  • Page 67

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) Table 3.5-2 Table of State Transition with Deep Standby Mode Enabled (Transition to and from Standby Mode) State transition Description After a reset, the device transits to main CR clock mode.

  • Page 68: Sleep Mode

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) 3.5.2 Sleep Mode In sleep mode, the operations of the CPU and watchdog timer are stopped. ■ Operations in Sleep Mode In sleep mode, the CPU and the operating clock for the watchdog timer are stopped. The CPU retains the contents of registers and RAM existing at the point immediately before the device transits to sleep mode and stops;...

  • Page 69: Stop Mode

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) 3.5.3 Stop Mode In stop mode, the main clock, the main CR clock, the main CR PLL clock and the subclock are stopped. ■ Operations in Stop Mode In stop mode, the main clock, the main CR clock, the main CR PLL clock and the subclock are stopped.

  • Page 70

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) Note: If the device is released from stop mode by an interrupt, a peripheral function having transited to stop mode during operation resumes operating from the point at which it transited to stop mode.

  • Page 71: Time-base Timer Mode

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) 3.5.4 Time-base Timer Mode In time-base timer mode, only the main clock oscillator, the subclock oscillator, the time-base timer, and the watch prescaler operate. The CPU and the operating clock for peripheral functions are stopped in this mode.

  • Page 72

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) Note: If the device is released from time-base timer mode by an interrupt, a peripheral function having transited to time-base timer mode during operation resumes operating from the point at which it transited to time-base timer mode.

  • Page 73: Watch Mode

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.5 Operations in Low Power Consumption Mode (Standby Mode) 3.5.5 Watch Mode In watch mode, only the subclock, the sub-CR clock and the watch prescaler operate. The CPU and the operating clock for peripheral functions are stopped in this mode.

  • Page 74: Clock Oscillator Circuit

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.6 Clock Oscillator Circuit Clock Oscillator Circuit The clock oscillator circuit generates an internal clock with an oscillator connected to the clock oscillation pin or by inputting a clock signal to the clock oscillation pin.

  • Page 75: Overview Of Prescaler

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.7 Overview of Prescaler Overview of Prescaler The prescaler generates the count clock source to be supplied to various peripheral functions from the machine clock (MCLK) and the count clock output from the time-base timer.

  • Page 76: Configuration Of Prescaler

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.8 Configuration of Prescaler Configuration of Prescaler Figure 3.8-1 is the block diagram of the prescaler. ■ Block Diagram of Prescaler Figure 3.8-1 Block Diagram of Prescaler Prescaler MCLK/2 MCLK/4 Counter value Count MCLK/8...

  • Page 77: Operation Of Prescaler

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.9 Operation of Prescaler Operation of Prescaler The prescaler generates count clock sources to different peripheral functions. ■ Operation of Prescaler The prescaler generates count clock sources from a clock whose frequency is generated by...

  • Page 78

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.9 Operation of Prescaler Table 3.9-3 Count Clock Sources Generated by Prescaler (F MCRPLL Frequency Frequency Frequency Frequency Count clock source = 8 MHz, = 10 MHz, = 12 MHz, = 16 MHz, MCRPLL...

  • Page 79: Notes On Using Prescaler

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.10 Notes on Using Prescaler 3.10 Notes on Using Prescaler This section provides notes on using the prescaler. The prescaler operates with the machine clock and the clock generated from the time-base timer, and keeps operating while those clocks are being supplied. Therefore, in the operation...

  • Page 80

    CHAPTER 3 CLOCK CONTROLLER MB95630H Series 3.10 Notes on Using Prescaler FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 81: Chapter 4 Reset

    CHAPTER 4 RESET This section describes the reset operation. Reset Operation Register Notes on Using Reset MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 82: Reset Operation

    CHAPTER 4 RESET MB95630H Series 4.1 Reset Operation Reset Operation When a reset source occurs, the CPU immediately stops the process being executed and enters the reset release wait state. When the reset is released, the CPU reads mode data and the reset vector from the Flash memory (mode fetch).

  • Page 83

    CHAPTER 4 RESET MB95630H Series 4.1 Reset Operation ● Low-voltage detection reset (optional) The circuit is only available on certain products. Check the availability of the circuit in the device data sheet. The low-voltage detection reset circuit generates a reset if the power supply voltage falls below a predetermined level.

  • Page 84

    CHAPTER 4 RESET MB95630H Series 4.1 Reset Operation ■ Overview of Reset Operation Figure 4.1-1 Reset Operation Flow Power-on reset/ External reset input low-voltage delection Software reset reset Watchdog reset Supress resets during RAM access Suppress resets during RAM access...

  • Page 85

    CHAPTER 4 RESET MB95630H Series 4.1 Reset Operation ■ Pin State During a Reset When a reset occurs, an I/O port or a peripheral resource pin remains high impedance until the setting of that I/O port or that peripheral resource pin by software is executed after the reset is released.

  • Page 86: Register

    CHAPTER 4 RESET MB95630H Series 4.2 Register Register This section provides details of the register for reset. Table 4.2-1 List of Register for Reset Register Register name Reference abbreviation RSRR Reset source register 4.2.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 87: Reset Source Register (rsrr), Reset Source Register (rsrr)

    CHAPTER 4 RESET MB95630H Series 4.2 Register 4.2.1 Reset Source Register (RSRR) The reset source register indicates the source of a reset generated. ■ Register Configuration Field — — — EXTS WDTR PONR Attribute — — — Initial value ■ Register Functions [bit7:5] Undefined bits Their read values are always "0".

  • Page 88

    CHAPTER 4 RESET MB95630H Series 4.2 Register [bit1] HWR: Hardware reset flag bit When this bit is set to "1", that indicates a hardware reset (power-on reset, low-voltage detection reset (optional), external reset or watchdog reset) other than software reset has occurred. Therefore, when any of bit2 to bit4 is set to "1", this bit is set to "1"...

  • Page 89

    CHAPTER 4 RESET MB95630H Series 4.2 Register ■ State of Reset Source Register (RSRR) Table 4.2-2 State of Reset Source Register Reset source EXTS WDTR PONR × × Power-on reset × × Low-voltage detection reset (optional) Software reset Watchdog reset...

  • Page 90: Notes On Using Reset

    CHAPTER 4 RESET MB95630H Series 4.3 Notes on Using Reset Notes on Using Reset This section provides notes on using the reset. ■ Notes on Using Reset ● Initialization of registers and bits by reset source Some registers and bits are initialized only by a certain reset source.

  • Page 91: Chapter 5 Interrupts

    CHAPTER 5 INTERRUPTS This chapter describes the interrupts. Interrupts MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 92: Interrupts

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts Interrupts This section describes the interrupts. ■ Overview of Interrupts The New 8FX family has 24 interrupt request inputs for respective peripheral functions, for each of which an interrupt level can be set independently to each other.

  • Page 93: Interrupt Level Setting Registers (ilr0 To Ilr5), Interrupt Level Setting Registers (ilr0 To Ilr)

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts 5.1.1 Interrupt Level Setting Registers (ILR0 to ILR5) The interrupt level setting registers (ILR0 to ILR5) contain 24 pairs of 2-bit data assigned to the interrupt requests of different peripheral functions. Each pair of bits (interrupt level setting bits) is used to set the interrupt level of an interrupt request.

  • Page 94

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts The interrupt level setting bits are compared with the interrupt level bits in the condition code register (CCR:IL[1:0]). If the interrupt level of an interrupt request is 3, the CPU ignores that interrupt request.

  • Page 95: Interrupt Processing

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts 5.1.2 Interrupt Processing When an interrupt request is made by a peripheral resource, the interrupt controller notifies the CPU of the interrupt level of that interrupt request. When the CPU is ready to accept interrupts, it halts the program it is executing and executes an interrupt service routine.

  • Page 96

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts (1) All interrupt requests are disabled immediately after a reset. In the peripheral resource initialization program, initialize those peripheral functions that generate interrupts and set their interrupt levels in their respective interrupt level setting registers (ILR0 to ILR5) before starting operating such peripheral functions.

  • Page 97: Nested Interrupts

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts 5.1.3 Nested Interrupts Different interrupt levels can be assigned to multiple interrupt requests from peripheral functions in the interrupt level setting registers (ILR0 to ILR5) to process nested interrupts. ■ Nested Interrupts During the execution of an interrupt service routine, if another interrupt request whose interrupt level has priority over the interrupt level of the interrupt being processed is made, the CPU suspends the current interrupt processing and accepts the interrupt request given priority.

  • Page 98: Interrupt Processing Time

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts 5.1.4 Interrupt Processing Time Before the CPU enters the interrupt service routine after an interrupt request is made, it needs to wait for the interrupt processing time, which consists of the time between the occurrence of an interrupt request and the end of the execution of the instruction being executed, and the interrupt handling time (the time required to initiate interrupt processing) to elapse.

  • Page 99: Stack Operation During Interrupt Processing

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts 5.1.5 Stack Operation During Interrupt Processing This section describes how the contents of a register are saved and restored during interrupt processing. ■ Stack Operation at the Start of Interrupt Processing Once the CPU accepts an interrupt, it automatically saves the current value of the program counter (PC) and that of the program status (PS) values to the stack.

  • Page 100: Interrupt Processing Stack Area

    CHAPTER 5 INTERRUPTS MB95630H Series 5.1 Interrupts 5.1.6 Interrupt Processing Stack Area The stack area in RAM is used for interrupt processing. The stack pointer (SP) contains the start address of the stack area. ■ Interrupt Processing Stack Area The stack area is also used for saving and restoring the program counter (PC) when the subroutine call instruction (CALL) or the vector call instruction (CALLV) is executed, and for saving temporarily and restoring register contents by the PUSHW and POPW instructions.

  • Page 101: Chapter 6 I/o Port, I/o Port

    CHAPTER 6 I/O PORT This chapter describes the configuration and operations of the I/O port. Overview Configuration and Operations MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 102

    CHAPTER 6 I/O PORT MB95630H Series 6.1 Overview Overview The I/O port is used to control general-purpose I/O pins. ■ Overview The I/O port has functions to output data from the CPU and capture input signals into the CPU with the port data register (PDR). The I/O direction of an individual I/O pin can be set as desired by using the corresponding to that I/O pin in the port direction register (DDR).

  • Page 103: Configuration And Operations

    CHAPTER 6 I/O PORT MB95630H Series 6.2 Configuration and Operations Configuration and Operations This section focuses on its configuration and operations as a general-purpose I/O port. For details of peripheral functions, see their respective chapters. ■ Configuration of I/O Port An I/O port is made up of the following elements.

  • Page 104

    CHAPTER 6 I/O PORT MB95630H Series 6.2 Configuration and Operations ■ Operations of I/O Port ● Operation as an output port • A pin becomes an output port if the bit in the DDRx register corresponding to that pin is set to "1".

  • Page 105

    CHAPTER 6 I/O PORT MB95630H Series 6.2 Configuration and Operations ● Operation at reset If the CPU is reset, all bits in the DDRx register are initialized to "0" and port input is enabled. As for a pin shared with analog input, its port input is disabled because the AIDRH/AIDRL register is initialized to "0".

  • Page 106

    CHAPTER 6 I/O PORT MB95630H Series 6.2 Configuration and Operations FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 107: Time-base Timer

    CHAPTER 7 TIME-BASE TIMER This chapter describes the functions and operations of the time-base timer. Overview Configuration Interrupt Operations and Setting Procedure Example Register Notes on Using Time-base Timer MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 108

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.1 Overview Overview The time-base timer is a 24-bit free-run down-counting counter. It is synchronized with the main clock divided by two or with the main CR clock or with the main CR PLL clock. The clock can be selected by the SCS[2:0] bits in the SYCC register.

  • Page 109: Configuration

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.2 Configuration Configuration The time-base timer consists of the following blocks: • Time-base timer counter • Counter clear circuit • Interval timer selector • Time-base timer control register (TBTC) ■ Block Diagram of Time-base Timer Figure 7.2-1 Block Diagram of Time-base Timer...

  • Page 110

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.2 Configuration ● Time-base timer counter This is a 24-bit downcounter using the main clock divided by two, the main CR clock, or the main CR PLL clock as its count clock. ● Counter clear circuit This circuit controls the clearing of the time-base timer counter.

  • Page 111: Interrupt

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.3 Interrupt Interrupt An interrupt request is generated when the interval time selected by the time- base timer elapses (interval timer function). ■ Interrupt When Interval Function Is in Operation When the time-base timer counter counts down by using the internal count clock and the time- base timer counter underflows due to the passage of the selected interval time, the time-base timer interrupt request flag bit (TBTC:TBIF) is set to "1".

  • Page 112: Operations And Setting Procedure Example

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.4 Operations and Setting Procedure Example Operations and Setting Procedure Example This section describes the operations of the interval timer function of the time- base timer. ■ Operations of Time-base Timer The counter of the time-base timer is initialized to "0xFFFFFF" after a reset, and starts counting while being synchronized with the main clock divided by two, the main CR clock, or the main CR PLL clock.

  • Page 113

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.4 Operations and Setting Procedure Example ■ Operation Examples of Time-base Timer Figure 7.4-2 shows examples of operations under the following conditions: 1. When a power-on reset is generated 2. When the device enters the sleep mode during the operation of the interval timer function in main clock mode, main CR clock mode or main CR PLL clock mode 3.

  • Page 114

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.4 Operations and Setting Procedure Example ■ Setting Procedure Example Below is an example of procedure for setting the time-base timer. ● Initial settings 1. Set the interrupt level. (ILR*) 2. Set the interval time. (TBTC:TBC[3:0]) 3.

  • Page 115

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.5 Register Register This section describes the register of the time-base timer. Table 7.5-1 List of Time-base Timer Register Register Register name Reference abbreviation TBTC Time-base timer control register 7.5.1 MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 116: Time-base Timer Control Register (tbtc), Time-base Timer Control Register (tbtc)

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.5 Register 7.5.1 Time-base Timer Control Register (TBTC) The time-base timer control register (TBTC) selects the interval time, clears the counter, controls interrupts and checks the status of the time-base timer. ■ Register Configuration...

  • Page 117

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.5 Register [bit4:1] TBC[3:0]: Interval time select bits These bits select interval time. Details Interval time Interval time Interval time bit4:1 (Main CR clock multiplied by (Main clock, (Main CR clock, a PLL multiplier of 2,...

  • Page 118: Notes On Using Time-base Timer

    CHAPTER 7 TIME-BASE TIMER MB95630H Series 7.6 Notes on Using Time-base Timer Notes on Using Time-base Timer This section provides notes on using the time-base timer. ■ Notes on Using Time-base Timer ● When setting the timer by program The timer cannot be waken up from interrupt processing when the time-base timer interrupt request flag bit (TBTC:TBIF) is set to "1"...

  • Page 119

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER This chapter describes the functions and operations of the watchdog timer. Overview Configuration Operations and Setting Procedure Example Register Notes on Using Watchdog Timer MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 120

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.1 Overview Overview The watchdog timer serves as a counter used to prevent programs from running out of control. ■ Watchdog Timer Function The watchdog timer functions as a counter used to prevent programs from running out of control.

  • Page 121

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.2 Configuration Configuration The watchdog timer consists of the following blocks: • Count clock selector • Watchdog timer counter • Reset control circuit • Watchdog timer clear selector • Counter clear control circuit •...

  • Page 122

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.2 Configuration ● Count clock selector This selector selects the count clock of the watchdog timer counter. ● Watchdog timer counter This is a 1-bit counter that uses the output of the time-base timer or of the watch prescaler or of the sub-CR timer as the count clock.

  • Page 123

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.3 Operations and Setting Procedure Example Operations and Setting Procedure Example The watchdog timer generates a watchdog reset when the watchdog timer counter overflows. ■ Operations of Watchdog Timer ● How to activate the watchdog timer Software watchdog •...

  • Page 124

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.3 Operations and Setting Procedure Example Note: The watchdog timer is also cleared when the timer selected as the count clock (time- base timer or watch prescaler) is cleared. For this reason, the watchdog timer cannot function if the software is set to repeatedly clear the timer selected as the count clock of the watchdog timer at the interval time selected for the watchdog timer.

  • Page 125

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.3 Operations and Setting Procedure Example ■ Setting Procedure Example Below is the procedure for setting the software watchdog timer. 1. Select the count clock. (WDTC:CS[1:0], CSP) 2. Activate the watchdog timer. (WDTC:WTE[3:0] = 0b0101) 3.

  • Page 126: Chapter 8 Hardware/software Watchdog Timer

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.4 Register Register This section describes the register of the watchdog timer. Table 8.4-1 List of Watchdog Timer Register Register Register name Reference abbreviation WDTC Watchdog timer control register 8.4.1 FUJITSU SEMICONDUCTOR LIMITED...

  • Page 127: Watchdog Timer Control Register (wdtc), Watchdog Timer Control Register (wdtc)

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.4 Register 8.4.1 Watchdog Timer Control Register (WDTC) The watchdog timer control register (WDTC) activates or clears the watchdog timer. ■ Register Configuration Field HWWDT WTE3 WTE2 WTE1 WTE0 Attribute and initial values for software watchdog timer...

  • Page 128

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.4 Register [bit3:0] WTE[3:0]: Watchdog control bits These bits controls the watchdog timer. The read value of these bits is always "0b0000". bit3:0 Details Activates the watchdog timer (in the first write access after a reset) or clears it (from the second write access after a reset).

  • Page 129: Notes On Using Watchdog Timer

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.5 Notes on Using Watchdog Timer Notes on Using Watchdog Timer This section provides notes on using the watchdog timer. ■ Notes on Using Watchdog Timer ● Stopping the watchdog timer Software watchdog timer Once activated, the watchdog timer cannot be stopped until a reset is generated.

  • Page 130

    CHAPTER 8 HARDWARE/SOFTWARE WATCHDOG TIMER MB95630H Series 8.5 Notes on Using Watchdog Timer FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 131

    CHAPTER 9 WATCH PRESCALER This chapter describes the functions and operations of the watch prescaler. Overview Configuration Interrupt Operations and Setting Procedure Example Register Notes on Using Watch Prescaler MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 132

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.1 Overview Overview The watch prescaler is a 16-bit down-counting, free-run counter, which is synchronized with the subclock divided by two or the sub-CR clock divided by two. It has an interval timer function that continuously generates interrupt requests at regular intervals.

  • Page 133

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.2 Configuration Configuration The watch prescaler consists of the following blocks: • Watch prescaler counter • Counter clear circuit • Interval timer selector • Watch prescaler control register (WPCR) ■ Block Diagram of Watch Prescaler Figure 9.2-1 Block Diagram of Watch Prescaler...

  • Page 134

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.2 Configuration ● Watch prescaler counter (counter) This is a 16-bit downcounter that uses the subclock divided by two or the sub-CR clock divided by two as its count clock. ● Counter clear circuit This circuit controls the clearing of the watch prescaler.

  • Page 135

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.3 Interrupt Interrupt An interrupt request is generated when the selected interval time of the watch prescaler has elapsed (interval timer function). ■ Interrupts in Operation of Interval Timer Function (Watch Prescaler Interrupts) In any mode except the stop mode in which the subclock mode or the sub-CR clock mode is...

  • Page 136

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.4 Operations and Setting Procedure Example Operations and Setting Procedure Example The watch prescaler operates as an interval timer. ■ Operations of Interval Timer Function (Watch Prescaler) The counter of the watch prescaler continues to count down using the subclock divided by two or the sub-CR clock divided by two as its count clock as long as the subclock or the sub-CR clock oscillates.

  • Page 137

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.4 Operations and Setting Procedure Example • In sub-CR clock mode Only the sub-CR clock is used as the input clock of the watch prescaler. ■ Operation Example of Watch Prescaler Figure 9.4-1 shows an operation example under the following conditions: 1.

  • Page 138

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.4 Operations and Setting Procedure Example ■ Setting Procedure Example Below is an example of procedure for setting the watch prescaler. ● Initial settings 1. Set the interrupt level. (ILR*) 2. Set the interval time. (WPCR:WTC[2:0]) 3.

  • Page 139

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.5 Register Register This section describes the register of the watch prescaler. Table 9.5-1 List of Watch Prescaler Register Register Register name Reference abbreviation WPCR Watch prescaler control register 9.5.1 MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 140: Watch Prescaler Control Register (wpcr), Watch Prescaler Control Register (wpcr)

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.5 Register 9.5.1 Watch Prescaler Control Register (WPCR) The watch prescaler control register (WPCR) is a register used to select the interval time, clear the counter, control interrupts and check the status of the watch prescaler.

  • Page 141

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.5 Register [bit3:1] WTC[2:0]: Watch prescaler interrupt interval time select bits These bits select the interval time. Details bit3:1 Interval time Interval time (Subclock, F = 32.768 kHz) (Sub-CR clock, F = 100 kHz) ×...

  • Page 142: Notes On Using Watch Prescaler

    CHAPTER 9 WATCH PRESCALER MB95630H Series 9.6 Notes on Using Watch Prescaler Notes on Using Watch Prescaler This section provides notes on using the watch prescaler. ■ Notes on Using Watch Prescaler ● When setting interrupt processing in a program The watch prescaler cannot be waken up from interrupt processing if the watch prescaler interrupt request flag bit (WPCR:WTIF) is set to "1"...

  • Page 143: Chapter 10 Wild Register Function

    CHAPTER 10 WILD REGISTER FUNCTION This chapter describes the functions and operations of the wild register function. 10.1 Overview 10.2 Configuration 10.3 Operations 10.4 Registers 10.5 Typical Hardware Connection Example MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 144

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.1 Overview 10.1 Overview The wild register function can be used to patch bugs in a program with addresses and amendment data, both of which are to be set in built-in registers. This section describes the wild register function.

  • Page 145

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.2 Configuration 10.2 Configuration The block diagram of the wild register is shown below. The wild register consists of the following blocks: • Memory area block Wild register data setting register (WRDR0 to WRDR2)

  • Page 146

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.2 Configuration ● Memory area block The memory area block consists of the wild register data setting registers (WRDR), wild register address setting registers (WRAR), wild register address compare enable register (WREN) and wild register data test setting register (WROR). The wild register function is used to specify the addresses and data that need to be replaced.

  • Page 147: Operations

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.3 Operations 10.3 Operations This section describes the procedure for setting the wild register function. ■ Procedure for Setting Wild Register Function Prepare a program that can read the value to be set in the wild register from external memory (e.g.

  • Page 148

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.4 Registers 10.4 Registers This section describes the registers of the wild register function. Table 10.4-1 List of Hardware/software Watchdog Timer Registers Register Register name Reference abbreviation WRDR0 Wild register data setting register 0 10.4.1...

  • Page 149: Wild Register Data Setting Registers (wrdr0 To Wrdr2)

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.4 Registers 10.4.1 Wild Register Data Setting Registers (WRDR0 to WRDR2) The wild register data setting registers (WRDR0 to WRDR2) use the wild register function to specify the data to be amended. ■ Register Configuration...

  • Page 150: Wild Register Address Setting Registers (wrar0 To Wrar2)

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.4 Registers 10.4.2 Wild Register Address Setting Registers (WRAR0 to WRAR2) The wild register address setting registers (WRAR0 to WRAR2) set the address to be amended by the wild register function. ■ Register Configuration...

  • Page 151: Wild Register Address Compare Enable Register (wren)

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.4 Registers 10.4.3 Wild Register Address Compare Enable Register (WREN) The wild register address compare enable register (WREN) enables or disables the operations of wild register functions using their respective wild register numbers.

  • Page 152: Wild Register Data Test Setting Register (wror), Wild Register Data Test Setting Register (wror)

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.4 Registers 10.4.4 Wild Register Data Test Setting Register (WROR) The wild register data test setting register (WROR) enables or disables data reading from the corresponding wild register data setting register (WRDR0 to WRDR2).

  • Page 153: Typical Hardware Connection Example

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.5 Typical Hardware Connection Example 10.5 Typical Hardware Connection Example Below is an example of typical hardware connection for the application of the wild register function. ■ Hardware Connection Example Figure 10.5-1 Typical Hardware Connection Example...

  • Page 154

    CHAPTER 10 WILD REGISTER FUNCTION MB95630H Series 10.5 Typical Hardware Connection Example FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 155

    11.9 Operation of PWM Timer Function (Fixed-cycle mode) 11.10 Operation of PWM Timer Function (Variable-cycle Mode) 11.11 Operation of PWC Timer Function 11.12 Operation of Input Capture Function 11.13 Operation of Noise Filter 11.14 Registers 11.15 Notes on Using 8/16-bit Composite Timer MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 156

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.1 Overview 11.1 Overview The 8/16-bit composite timer consists of two 8-bit counters. It can be used as two 8-bit timers, or as a 16-bit timer if the two counters are connected in cascade.

  • Page 157

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.1 Overview ■ PWC Timer Function When the PWC timer function is selected, the width and cycle of an external input pulse can be measured. In this operating mode, the counter starts counting from "0x00" immediately after a count start edge of an external input signal is detected.

  • Page 158

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.2 Configuration 11.2 Configuration The 8/16-bit composite timer consists of the following blocks: • 8-bit counter • 8-bit comparator (including a temporary latch) • 8/16-bit composite timer data register (Tn0DR/Tn1DR) • 8/16-bit composite timer status control register 0 (Tn0CR0/Tn1CR0) •...

  • Page 159

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.2 Configuration ■ Block Diagram of 8/16-bit Composite Timer Figure 11.2-1 Block Diagram of 8/16-bit Composite Timer Tn0CR0 IFE C2 C1 C0 F2 F1 F0 Timer n0 CK00 8-bit counter Clocks from prescaler/...

  • Page 160

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.2 Configuration ● 8/16-bit composite timer data register (Tn0DR/Tn1DR) These registers are used to write the maximum value counted during interval timer operation or PWM timer operation and to read the count value during PWC timer operation or input capture operation.

  • Page 161: Channel

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.3 Channel 11.3 Channel This section describes the channels of the 8/16-bit composite timer. ■ Channel of 8/16-bit Composite Timer On a channel, there are two 8-bit counters. They can be used as two 8-bit timers or one 16-bit timer.

  • Page 162: Pins

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.4 Pins 11.4 Pins This section describes the pins of the 8/16-bit composite timer. ■ Pins of 8/16-bit Composite Timer The external pins of the 8/16-bit composite timer are TOn0, TOn1 and ECn. TII0 is for internal chip connection.

  • Page 163

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.5 Interrupts 11.5 Interrupts The 8/16-bit composite timer generates the following types of interrupts. An interrupt number and an interrupt vector are assigned to each type of interrupts. • Timer n0 interrupt • Timer n1 interrupt ■...

  • Page 164: Operation Of Interval Timer Function (one-shot Mode), Operation Of Interval Timer Function (one-shot Mode)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.6 Operation of Interval Timer Function (One-shot Mode) 11.6 Operation of Interval Timer Function (One-shot Mode) This section describes the operation of the interval timer function (one-shot mode) of the 8/16-bit composite timer.

  • Page 165

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.6 Operation of Interval Timer Function (One-shot Mode) Figure 11.6-2 Operation of Interval Timer Function in 8-bit Operation (One-shot Mode) Counter value 0xFF 0x80 0x00 Time Timer cycle Tn0DR/Tn1DR value modified (0xFF→0x80)* Tn0DR/Tn1DR...

  • Page 166: Operation Of Interval Timer Function (continuous Mode)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.7 Operation of Interval Timer Function (Continuous Mode) 11.7 Operation of Interval Timer Function (Continuous Mode) This section describes the interval timer function (continuous mode operation) of the 8/16-bit composite timer. ■ Operation of Interval Timer Function (Continuous Mode) The register settings shown in Figure 11.7-1 are required to use interval timer function...

  • Page 167

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.7 Operation of Interval Timer Function (Continuous Mode) Figure 11.7-2 Operation Diagram of Interval Timer Function (Continuous Mode) Compare value Compare value Compare value Compare value (0xE0) (0xFF) (0x80) 0xFF 0xE0 0x80 0x00...

  • Page 168: Operation Of Interval Timer Function (free-run Mode), Operation Of Interval Timer Function (free-run Mode)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.8 Operation of Interval Timer Function (Free-run Mode) 11.8 Operation of Interval Timer Function (Free-run Mode) This section describes the operation of the interval timer function (free-run mode) of the 8/16-bit composite timer.

  • Page 169

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.8 Operation of Interval Timer Function (Free-run Mode) Figure 11.8-2 Operation Diagram of Interval Timer Function (Free-run Mode) (0xE0) Counter value 0xFF 0xE0 0x80 0x00 Time Tn0DR/Tn1DR value (0xE0) Cleared by program IF bit...

  • Page 170: Operation Of Pwm Timer Function (fixed-cycle Mode), Operation Of Pwm Timer Function (fixed-cycle Mode)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.9 Operation of PWM Timer Function (Fixed-cycle mode) 11.9 Operation of PWM Timer Function (Fixed-cycle mode) This section describes the operation of the PWM timer function (fixed-cycle mode) of the 8/16-bit composite timer.

  • Page 171

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.9 Operation of PWM Timer Function (Fixed-cycle mode) Figure 11.9-2 Operation Diagram of PWM Timer Function (Fixed-cycle Mode) Tn0DR/Tn1DR register value: "0x00" (duty ratio = 0%) Counter value 0x00 0xFF 0x00 "H" PWM waveform "L"...

  • Page 172: Operation Of Pwm Timer Function (variable-cycle Mode)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.10 Operation of PWM Timer Function (Variable-cycle Mode) 11.10 Operation of PWM Timer Function (Variable-cycle Mode) This section describes the operation of the PWM timer function (variable-cycle mode) of the 8/16-bit composite timer.

  • Page 173

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.10 Operation of PWM Timer Function (Variable-cycle Mode) Figure 11.10-2 Operation Diagram of PWM Timer Function (Variable-cycle Mode) Tn0DR register value: "0x80", Tn1DR register value: "0x80" (duty ratio = 0%) (timer n0 value ≥ timer n1 value)

  • Page 174: Operation Of Pwc Timer Function

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.11 Operation of PWC Timer Function 11.11 Operation of PWC Timer Function This section describes the operation of the PWC timer function of the 8/16-bit composite timer. ■ Operation of PWC Timer Function The settings shown in Figure 11.11-1 are required to use the PWC timer function.

  • Page 175

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.11 Operation of PWC Timer Function Figure 11.11-2 Operation Diagram of PWC Timer (Example of H-pulse Width Measurement) "H" width Pulse input (Input waveform to PWC pin) Counter value 0xFF Time Cleared by program...

  • Page 176: Operation Of Input Capture Function

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.12 Operation of Input Capture Function 11.12 Operation of Input Capture Function This section describes the operation of the input capture function of the 8/16- bit composite timer. ■ Operation of Input Capture Function The settings shown in Figure 11.12-1 are required to use the input capture function.

  • Page 177

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.12 Operation of Input Capture Function Note: See "11.15 Notes on Using 8/16-bit Composite Timer" for notes on using the input capture function. Figure 11.12-2 Operating Diagram of Input Capture Function 0xFF 0xBF...

  • Page 178: Operation Of Noise Filter

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.13 Operation of Noise Filter 11.13 Operation of Noise Filter This section describes the operation of the noise filter of the 8/16-bit composite timer. When the input capture function or PWC timer function is selected, a noise filter can be used to eliminate the pulse noise of the signal from the external input pin (ECn).

  • Page 179

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers 11.14 Registers This section describes the registers of the 8/16-bit composite timer. Table 11.14-1List of 8/16-bit Composite Timer Registers Register Register name Reference abbreviation Tn0CR0 8/16-bit composite timer n0 status control register 0 11.14.1...

  • Page 180: Bit Composite Timer Status Control Register 0 (tn0cr0/tn1cr0)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers 11.14.1 8/16-bit Composite Timer Status Control Register 0 (Tn0CR0/Tn1CR0) The 8/16-bit composite timer status control register 0 (Tn0CR0/Tn1CR0) selects the timer operation mode, selects the count clock, and enables or disables IF flag interrupts.

  • Page 181

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit6:4] C[2:0]: Count clock select bits These bits select the count clock. The count clock is generated by the prescaler. See "3.9 Operation of Prescaler". During timer operation (Tn0CR1/Tn1CR1:STA = 1), the write access to these bits has no effect on operation in timer operation.

  • Page 182

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit3:0] F[3:0]: Timer operating mode select bits These bits select the timer operating mode. The PWM timer function (variable-cycle mode; F[3:0] = 0b0100) is set by either the Tn0CR0 (timer n0) register or Tn1CR0 (timer n1) register.

  • Page 183: Bit Composite Timer Status Control Register 1 (tn0cr1/tn1cr1)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers 11.14.2 8/16-bit Composite Timer Status Control Register 1 (Tn0CR1/Tn1CR1) The 8/16-bit composite timer status control register 1 (Tn0CR1/Tn1CR1) controls the interrupt flag, timer output, and timer operations. Tn0CR1 and Tn1CR1 registers correspond to timers n0 and n1 respectively.

  • Page 184

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit6] HO: Timer suspend bit This bit suspends or resumes the timer operation. Writing "1" to this bit during timer operation suspends the timer operation. When the timer operation has been enabled (Tn0CR1/Tn1CR1:STA = 1), writing "0" to the bit resumes the timer operation.

  • Page 185

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit3] BF: Data register full flag With the PWC timer function in use, this bit is set to "1" when a count value is stored in the 8/16-bit composite timer data register (Tn0DR/Tn1DR) immediately after pulse width measurement is complete.

  • Page 186

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit1] SO: Timer output initial value bit The timer output (TMCRn:TO1/TO0) initial value is set by writing a value to this bit. The value in this bit is reflected in the timer output when the timer operation enable bit (Tn0CR1/Tn1CR1:STA) changes from "0"...

  • Page 187: Bit Composite Timer Timer Mode Control Register (tmcrn)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers 11.14.3 8/16-bit Composite Timer Timer Mode Control Register (TMCRn) The 8/16-bit composite timer timer mode control register (TMCRn) selects the filter function, 8-bit or 16-bit operating mode, and signal input to timer n0 and indicates the timer output value.

  • Page 188

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit5] TIS: Timer n0 internal signal select bit This bit selects the signal input to timer n0 when the PWC timer function or input capture function is selected. The functions of this bit vary among channels. Details of the functions for different channels are explained below.

  • Page 189

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers [bit1:0] FE0[1:0]: Timer n0 filter function select bits These bits select the filter function for the external signal (ECn) to timer n0 when the PWC timer function or the input capture function is selected.

  • Page 190: Bit Composite Timer Data Register (tn0dr/tn1dr)

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers 11.14.4 8/16-bit Composite Timer Data Register (Tn0DR/ Tn1DR) The 8/16-bit composite timer data register (Tn0DR/Tn1DR) is used to set the maximum count value during the interval timer operation or the PWM timer operation and to read the count value during the PWC timer operation or the input capture operation.

  • Page 191

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers ● PWM timer function (variable-cycle) The 8/16-bit composite timer n0 data register (Tn0DR) and 8/16-bit composite timer n1 data register (Tn1DR) are used to set "L" pulse width time and cycle respectively. When the timer starts operating (Tn0CR1/Tn1CR1:STA = 1), the value of each register is transferred to the latch in the 8-bit comparator and the two counters start counting from timer output "L".

  • Page 192

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.14 Registers ● Read and write operations Read and write operations of Tn0DR and Tn1DR are performed in the following manner in 16- bit operation or when the PWM timer function (variable-cycle) is selected.

  • Page 193: Notes On Using 8/16-bit Composite Timer

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.15 Notes on Using 8/16-bit Composite Timer 11.15 Notes on Using 8/16-bit Composite Timer This section provides notes on using the 8/16-bit composite timer. ■ Notes on Using 8/16-bit Composite Timer • To switch the timer function with the timer operating mode select bits (Tn0CR0/...

  • Page 194

    CHAPTER 11 8/16-BIT COMPOSITE TIMER MB95630H Series 11.15 Notes on Using 8/16-bit Composite Timer Figure 11.15-1 Operations of Counter in Standby Mode or in Pause (Not Serving as PWM Timer) Tn0DR/Tn1DR data register value (0xFF) Counter value 0xFF 0x80 0x00...

  • Page 195: Chapter 12 External Interrupt Circuit

    This chapter describes the functions and operations of the external interrupt circuit. 12.1 Overview 12.2 Configuration 12.3 Channels 12.4 Pin 12.5 Interrupt 12.6 Operations and Setting Procedure Example 12.7 Register 12.8 Notes on Using External Interrupt Circuit MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 196

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.1 Overview 12.1 Overview The external interrupt circuit detects edges on the signal that is input to the external interrupt pin, and outputs interrupt requests to the interrupt controller. ■ Function of External Interrupt Circuit The external interrupt circuit detects any edge of a signal that is input to an external interrupt pin and generates interrupt requests to the interrupt controller.

  • Page 197

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.2 Configuration 12.2 Configuration The external interrupt circuit consists of the following blocks: • Edge detection circuit • External interrupt control register ■ Block Diagram of External Interrupt Circuit Figure 12.2-1 is the block diagram of the external interrupt circuit.

  • Page 198: Channels

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.3 Channels 12.3 Channels This section describes the channels of the external interrupt circuit. ■ Channels of External Interrupt Circuit Table 12.3-1 shows the pins and their corresponding registers of the external interrupt.

  • Page 199

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.4 Pin 12.4 This section provides details of the pin of the external interrupt circuit. ■ Pin of External Interrupt Circuit ● INT pin This pin serves both as an external interrupt input pin and as a general-purpose I/O port.

  • Page 200

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.5 Interrupt 12.5 Interrupt The interrupt source for the external interrupt circuit is the detection of the specified edge of the signal input to an external interrupt pin. ■ Interrupt during Operation of External Interrupt Circuit When the specified edge of external interrupt input is detected, the corresponding external interrupt request flag bit (EIC:EIR0 or EIR1) is set to "1".

  • Page 201

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.6 Operations and Setting Procedure Example 12.6 Operations and Setting Procedure Example This section describes the operations of the external interrupt circuit. ■ Operations of External Interrupt Circuit When the polarity of an edge of a signal input from one of the external interrupt pins (INTn,...

  • Page 202

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.6 Operations and Setting Procedure Example ■ Setting Procedure Example Below is an example of procedure for setting the external interrupt circuit. ● Initial settings 1. Set the interrupt level. (ILR*) 2. Select the edge polarity. (EIC:SL0[1:0]) 3.

  • Page 203

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.7 Register 12.7 Register This section describes the register of the external interrupt circuit. Table 12.7-1 List of External Interrupt Circuit Register Register Register name Reference abbreviation External interrupt control register 12.7.1 MN702-00009-1v0-E...

  • Page 204: External Interrupt Control Register (eic), External Interrupt Control Register (eic)

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.7 Register 12.7.1 External Interrupt Control Register (EIC) The external interrupt control register (EIC) is used to select the edge polarity for the external interrupt input and control interrupts. ■ Register Configuration Field...

  • Page 205

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.7 Register [bit3] EIR0: External interrupt request flag bit 0 This flag is set to "1" when the edge selected by the edge polarity select bits 0 (SL0[1:0]) is input to the external interrupt pin INTn.

  • Page 206: Notes On Using External Interrupt Circuit

    CHAPTER 12 EXTERNAL INTERRUPT CIRCUIT MB95630H Series 12.8 Notes on Using External Interrupt Circuit 12.8 Notes on Using External Interrupt Circuit This section provides notes on using the external interrupt circuit. ■ Notes on Using External Interrupt Circuit • Before setting the edge polarity select bits (SL0[1:0] or SL1[1:0]), set the interrupt request enable bit (EIE0 or EIE1) to "0"...

  • Page 207: Chapter 13 Interrupt Pin Selection Circuit

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT This chapter describes the functions and operations of the interrupt pin selection circuit. 13.1 Overview 13.2 Configuration 13.3 Pins 13.4 Operation 13.5 Register 13.6 Notes on Using Interrupt Pin Selection Circuit MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 208

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.1 Overview 13.1 Overview The interrupt pin selection circuit selects pins to be used as interrupt input pins from among various peripheral input pins. ■ Interrupt Pin Selection Circuit The interrupt pin selection circuit is used to select interrupt input pins from various peripheral inputs (EC1, INT00, TRG1, UCK0 and UI0).

  • Page 209

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.2 Configuration 13.2 Configuration Figure 13.2-1 shows the block diagram of the interrupt pin selection circuit. ■ Block Diagram of Interrupt Pin Selection Circuit Figure 13.2-1 Block Diagram of Interrupt Pin Selection Circuit...

  • Page 210

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.3 Pins 13.3 Pins This section describes the pins of the interrupt pin selection circuit. ■ Pins of Interrupt Pin Selection Circuit The peripheral function pins of the interrupt pin selection circuit are the EC1, INT00, TRG1, UCK0 and UI0 pins.

  • Page 211: Operation

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.4 Operation 13.4 Operation The interrupt pins are selected by setting the WICR register. ■ Operation of Interrupt Pin Selection Circuit The WICR register selects the input pins to be input to INT00 of the external interrupt circuit (ch.

  • Page 212

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.5 Register 13.5 Register This section describes the register of the interrupt pin selection circuit. Table 13.5-1 List of External Interrupt Circuit Register Register Register name Reference abbreviation WICR Interrupt pin selection circuit control register 13.5.1...

  • Page 213: Interrupt Pin Selection Circuit Control Register (wicr)

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.5 Register 13.5.1 Interrupt Pin Selection Circuit Control Register (WICR) This register is used to determine which of the available peripheral input pins should be output to the interrupt circuit and which interrupt pins they should serve as.

  • Page 214

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.5 Register [bit2] UI0: UI0 interrupt pin select bit This bit determines whether to select the UI0 pin as an interrupt input pin. Writing "0" to this bit deselects the UI0 pin as an interrupt input pin, and the interrupt pin selection circuit treats the UI0 pin input as being fixed at "0".

  • Page 215

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.5 Register Note: The input signals to the peripheral pins do not generate an external interrupt even when "1" is written to these bits if the INT00 (ch. 0) of the external interrupt circuit is disabled.

  • Page 216: Notes On Using Interrupt Pin Selection Circuit

    CHAPTER 13 INTERRUPT PIN SELECTION CIRCUIT MB95630H Series 13.6 Notes on Using Interrupt Pin Selection Circuit 13.6 Notes on Using Interrupt Pin Selection Circuit This section provides notes on using the interrupt pin selection circuit. • If multiple interrupt pins are selected in the WICR register simultaneously and the operation of INT00 (ch.

  • Page 217: Chapter 14 Lin-uart

    This chapter describes the functions and operations of the LIN-UART. 14.1 Overview 14.2 Configuration 14.3 Pins 14.4 Interrupts 14.5 LIN-UART Baud Rate 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.7 Registers 14.8 Notes on Using LIN-UART MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 218

    CHAPTER 14 LIN-UART MB95630H Series 14.1 Overview 14.1 Overview The LIN (Local Interconnect Network)-UART is a general-purpose serial data communication interface for synchronous or asynchronous (start-stop synchronization) communication with external devices. In addition to a bi- directional communication function (normal...

  • Page 219

    CHAPTER 14 LIN-UART MB95630H Series 14.1 Overview The LIN-UART operates in four different modes. The operating mode is selected by the MD0 and MD1 bits in the LIN-UART serial mode register (SMR). Operating mode 0 and operating mode 2 are used for bi-directional serial communication; operating mode 1 for master/slave communication;...

  • Page 220

    CHAPTER 14 LIN-UART MB95630H Series 14.2 Configuration 14.2 Configuration LIN-UART is made up of the following blocks. • Reload counter • Receive control circuit • Receive shift register • LIN-UART receive data register (RDR) • Transmit control circuit • Transmit shift register •...

  • Page 221: Reload Counter

    CHAPTER 14 LIN-UART MB95630H Series 14.2 Configuration ■ Block Diagram of LIN-UART Figure 14.2-1 Block Diagram of LIN-UART OTO, ORE FRE Machine EXT, REST clock Transmit clock Reload LBIE Receive clock Interrupt Transmit counter generation Receive control control circuit circuit...

  • Page 222

    CHAPTER 14 LIN-UART MB95630H Series 14.2 Configuration ● Receive control circuit This block consists of a receive bit counter, a start bit detection circuit, and a receive parity counter. The receive bit counter counts the receive data bits and sets a flag in the LIN-UART receive data register when the reception of one data is completed according to the specified data length.

  • Page 223

    CHAPTER 14 LIN-UART MB95630H Series 14.2 Configuration ● LIN synch break/synch field detection circuit This circuit detects a LIN synch break when the LIN master node transmits a message header. The LBD flag is set when the LIN synch break is detected. An internal signal is output to 8/16- bit composite timer in order to detect the first and the fifth falling edges of the LIN synch field and to measure the actual serial clock synchronization transmitted by the master node.

  • Page 224

    CHAPTER 14 LIN-UART MB95630H Series 14.2 Configuration ● Extended status control register (ESCR) Its operating functions are as follows: • Enabling/disabling LIN synch break interrupts • LIN synch break detection • Selecting LIN synch break length • Direct access to SIN pin and SOT pin •...

  • Page 225

    CHAPTER 14 LIN-UART MB95630H Series 14.3 Pins 14.3 Pins This section describes the pins of the LIN-UART. ■ Pins of LIN-UART The pins of the LIN-UART are also used as general-purpose ports. Table 14.3-1 lists the LIN- UART pin functions and settings for using them.

  • Page 226

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts 14.4 Interrupts The LIN-UART has receive interrupts and transmit interrupts, which are generated by the following sources. An interrupt number and an interrupt vector are assigned to each interrupt. In addition, it has a LIN synch field edge detection interrupt function using the 8/16-bit composite timer interrupt.

  • Page 227

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts A receive interrupt request is made if the receive interrupt has been enabled (SSR:RIE = 1) when one of the above flag bits is "1". RDRF flag is automatically cleared to "0" if the LIN-UART receive data register (RDR) is read.

  • Page 228

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts ■ LIN Synch Field Edge Detection Interrupt (8/16-bit Composite Timer Interrupt) Table 14.4-3 shows the control bits and interrupt sources of the LIN synch field edge detection interrupt. Table 14.4-3 Interrupt Control Bits and Interrupt Sources of LIN Synch Field Edge Detection...

  • Page 229: Timing Of Receive Interrupt Generation And Flag Set

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts 14.4.1 Timing of Receive Interrupt Generation and Flag A receive interrupt is generated when reception is completed (SSR:RDRF) or when a reception error occurs (SSR:PE, ORE, FRE). ■ Timing of Receive Interrupt Generation and Flag Set...

  • Page 230

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts Figure 14.4-3 ORE Flag Set Timing Received data ST 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 SP RDRF FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 231: Timing Of Transmit Interrupt Generation And Flag Set

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts 14.4.2 Timing of Transmit Interrupt Generation and Flag A transmit interrupt is generated when transmit data is transferred from the LIN-UART transmit data register (TDR) to the transmit shift register and then data transmission starts.

  • Page 232

    CHAPTER 14 LIN-UART MB95630H Series 14.4 Interrupts ■ Transmit Interrupt Request Generation Timing With the transmit interrupt having been enabled (SSR:TIE = 1), if the TDRE bit is set to "1", a transmit interrupt is generated. Note: Since the initial value of the TDRE bit is "1", a transmit interrupt is generated immediately after the transmit interrupt is enabled (SSR:TIE = 1).

  • Page 233: Lin-uart Baud Rate

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate 14.5 LIN-UART Baud Rate The input clock (transmit/receive clock source) of the LIN-UART can be selected from one of the following: • Input a machine clock to a baud rate generator (reload counter).

  • Page 234

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate Figure 14.5-1 LIN-UART Baud Rate Selection Circuit REST Start bit falling Reload value: v edge detection Receive Rxc = 0? Receive clock 15-bit reload counter Reload Reset Rxc = v/2? Reload value: v...

  • Page 235: Baud Rate Setting

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate 14.5.1 Baud Rate Setting This section shows baud rate settings and the result of calculating the serial clock frequency. ■ Baud Rate Calculation The two 15-bit reload counters are set by the LIN-UART baud rate generator registers 1, 0 (BGR1, BGR0).

  • Page 236

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate ■ Reload Value and Baud Rate of Each Clock Speed Table 14.5-1 shows the reload value and baud rate of each clock speed. Table 14.5-1 Reload Value and Baud Rate 8 MHz (MCLK)

  • Page 237

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate ■ External Clock The external clock is selected by writing "1" to the EXT bit in the LIN-UART serial mode register (SMR). In the baud rate generator, the external clock can be used in the same way as the internal clock.

  • Page 238

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate ■ Operation of Dedicated Baud Rate Generator (Reload Counter) Figure 14.5-2 shows the operation of two reload counters using a reload value "832" as an example. Figure 14.5-2 Operation of Dedicated Baud Rate Generator (Reload Counter)

  • Page 239: Reload Counter

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate 14.5.2 Reload Counter This block is a 15-bit reload counter functioning as a dedicated baud rate generator. It generates the transmit/receive clock from the external clock or internal clock. The count value in the transmit reload counter can be read from the LIN-UART baud rate generator registers 1, 0 (BGR1 and BGR0).

  • Page 240

    CHAPTER 14 LIN-UART MB95630H Series 14.5 LIN-UART Baud Rate Figure 14.5-3 Example of Using a Simple Timer by Restarting the Reload Timer MCLK (Machine clock) Write SMR register REST bit write signal Reload Reload counter 37 36 35 100 99 98 97 96 95 94 93 92 91 90 89 88 87...

  • Page 241: Operations Of Lin-uart And Lin-uart Setting Procedure Example

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example The LIN-UART performs bi-directional serial communication in operating mode 0/2, master/slave communication in operating mode 1, LIN master/slave communication in operating mode 3.

  • Page 242

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ■ Inter-CPU Connection Method The external clock one-to-one connection (normal mode) and the master/slave connection (multiprocessor mode) can be selected as an inter-CPU connection method. In either method, CPUs must use the same data length, parity setting, synchronization type, etc.

  • Page 243: Operations In Asynchronous Mode (operating Mode 0, 1)

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.1 Operations in Asynchronous Mode (Operating Mode 0, 1) When the LIN-UART is used in operating mode 0 (normal mode) or operating mode 1 (multiprocessor mode), the transfer method is asynchronous transfer.

  • Page 244

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example Figure 14.6-1 Transmit/Receive Data Format (Operating Mode 0, 1) [Operating mode 0] ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP P: None ST D0...

  • Page 245

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ● Transmission If the transmit data register empty flag bit (TDRE) in the LIN-UART serial status register (SSR) is "1", transmit data can be written to the LIN-UART transmit data register (TDR).

  • Page 246

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ● Stop bit and reception bus idle flag For transmission, the number of stop bits can be selected from one and two. If two stop bits are selected, both stop bits are detected during reception.

  • Page 247: Operations In Synchronous Mode (operating Mode 2), Operations In Synchronous Mode (operating Mode)

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.2 Operations in Synchronous Mode (Operating Mode 2) When the LIN-UART is used in operating mode 2 (normal mode), the transfer method is clock-synchronous transfer. ■ Operations in Synchronous Mode (Operating Mode 2) ●...

  • Page 248

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ● Clock supply In clock synchronous mode (normal), the number of transmit/receive data bits must be equal to the number of clock cycles. When the start/stop bits are enabled, the number of clock cycles must be equal to the sum of the transmit/receive data bits and the added start/stop bits.

  • Page 249

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ● Continuous clock supply When the CCO bit in the ESCR register is "1", the serial clock output from the SCK pin is continuously supplied on the serial clock transmission side. In this case, add the start bit and the stop bit to the data format (SSM = 1) in order to identify the beginning and end of the data frame.

  • Page 250

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example • LIN-UART serial status register (SSR) BDS : "0"– LSB-first, "1"– MSB-first RIE : "1"– Enables receive interrupts, "0"– Disables receive interrupts TIE : "1"– Enables transmit interrupts, "0"– Disables transmit interrupts •...

  • Page 251: Operations Of Lin Function (operating Mode 3), Operations Of Lin Function (operating Mode)

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.3 Operations of LIN function (Operating Mode 3) In operating mode 3, the LIN-UART works as the LIN master and the LIN slave. In operating mode 3, the communication format is set to 8-bit data, no parity, stop bit 1, LSB first.

  • Page 252

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example Find the baud rate setting with the following equations. When the counter of the 8/16-bit composite timer does not overflow : BGR value = (b - a) / 8 - 1...

  • Page 253

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example Figure 14.6-8 LIN-UART Operation in LIN Slave Mode Serial clock cycle# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15...

  • Page 254: Serial Pin Direct Access

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.4 Serial Pin Direct Access The transmit pin (SOT) and the receive pin (SIN) can be accessed directly. ■ LIN-UART Pin Direct Access The LIN-UART allows the programmer to directly access the serial I/O pins.

  • Page 255: Bidirectional Communication Function (normal Mode)

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.5 Bidirectional Communication Function (Normal Mode) Normal serial bidirectional communication can be performed in operating mode 0 or 2. Asynchronous mode can be selected in operating mode 0 and synchronous mode in operating mode 2.

  • Page 256

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ● Communication procedure example The communication starts from the transmit side at any time after transmit data is ready. The receive side returns ANS (per one byte in this example) regularly after receiving transmit data.

  • Page 257: Master/slave Mode Communication Function (multiprocessor Mode)

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.6 Master/Slave Mode Communication Function (Multiprocessor Mode) Operating mode 1 allows communication among multiple CPUs connected in master/slave mode. The LIN-UART can be used as a master or a slave.

  • Page 258

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example Table 14.6-4 Selection of Master/Slave Mode Communication Functions Operating mode Synchronous Data Parity Stop bit Bit direction method Master CPU Slave CPU Address AD = 1...

  • Page 259

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example Figure 14.6-15 Master/Slave Mode Communication Flow Chart (Master CPU) (Slave CPU) Start Start Set to operating mode 1 Set to operating mode 1 Set SIN pin for serial data Set SIN pin for serial data input.

  • Page 260: Lin Communication Function

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.7 LIN Communication Function In LIN-UART communication, a LIN device can be used in a LIN master system or a LIN slave system. ■ LIN Master/Slave Mode Communication Function Figure 14.6-16 shows the required settings for the LIN communication mode (operating mode...

  • Page 261: Examples Of Lin-uart Lin Communication Flow Chart (operating Mode 3)

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example 14.6.8 Examples of LIN-UART LIN Communication Flow Chart (Operating Mode 3) This section shows examples of LIN-UART LIN communication flow charts. ■ LIN Master Device Figure 14.6-18 LIN Master Flow Chart...

  • Page 262

    CHAPTER 14 LIN-UART MB95630H Series 14.6 Operations of LIN-UART and LIN-UART Setting Procedure Example ■ LIN Slave Device Figure 14.6-19 LIN Slave Flow Chart Start Initial setting: Set to operating mode 3 Enable serial data output TXE = 1, TIE = 0, RXE = 0, RIE = 1...

  • Page 263

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7 Registers This section describes the registers of the LIN-UART. Table 14.7-1 List of LIN-UART Registers Register Register name Reference abbreviation LIN-UART serial control register 14.7.1 LIN-UART serial mode register 14.7.2 LIN-UART serial status register 14.7.3...

  • Page 264: Lin-uart Serial Control Register (scr), Lin-uart Serial Control Register (scr)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.1 LIN-UART Serial Control Register (SCR) The LIN-UART serial control register (SCR) is used to set parity, select the stop bit length and data length, select the frame data format in operating mode 1, clear the receive error flag, and enable/disable transmission/reception.

  • Page 265

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers [bit4] CL: Data length select bit This bit specifies the data length to be transmitted and received. This bit is fixed at "1" in operating mode 2 and operating mode 3. bit4 Details Writing "0"...

  • Page 266: Lin-uart Serial Mode Register (smr), Lin-uart Serial Mode Register (smr)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.2 LIN-UART Serial Mode Register (SMR) The LIN-UART serial mode register (SMR) is used to select the operating mode, specify the baud rate clock, and enable/disable output to the serial data and clock pins.

  • Page 267

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers [bit2] UPCL: LIN-UART programmable clear bit (LIN-UART software reset) This bit resets the LIN-UART. Writing "0" to this bit has no effect on operation. Writing "1" to this bit resets the LIN-UART immediately (LIN-UART software reset). However, the register settings are maintained.

  • Page 268: Lin-uart Serial Status Register (ssr), Lin-uart Serial Status Register (ssr)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.3 LIN-UART Serial Status Register (SSR) The LIN-UART serial status register (SSR) is used to check the status of transmission, reception and error, and to enable and disable interrupts. ■ Register Configuration Field...

  • Page 269

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers [bit4] RDRF: Receive data register full flag bit This flag bit shows the status of the LIN-UART receive data register (RDR). This bit is set to "1" when received data is loaded into RDR, and cleared to "0" by reading the receive data register (RDR).

  • Page 270: Lin-uart Receive Data Register/lin-uart Transmit Data Register (rdr/tdr)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.4 LIN-UART Receive Data Register/LIN-UART Transmit Data Register (RDR/TDR) The LIN-UART receive data register and the LIN-UART transmit data register are located at the same address. If read, they function as the receive data register;...

  • Page 271

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers Note: The LIN-UART transmit data register is a write-only register; the receive data register is a read-only register. Since both registers are located at the same address, the write value and the read value are different. Thus, the read-modify-write (RMW) type of instruction, such as the INC instruction and the DEC instruction, cannot be used.

  • Page 272: Lin-uart Extended Status Control Register (escr)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.5 LIN-UART Extended Status Control Register (ESCR) The LIN-UART extended status control register (ESCR) has the settings for enabling/disabling LIN synch break interrupt, LIN synch break length selection, LIN synch break detection, direct access to the SIN and SOT pins, continuous clock output in LIN-UART synchronous clock mode and sampling clock edge.

  • Page 273

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers [bit5:4] LBL[1:0]: LIN synch break length select bits These bits select the bit length for the LIN synch break generation time. The LIN synch break length for reception is always 11 bits. bit5:4 Details Writing "00"...

  • Page 274

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers [bit1] CCO: Continuous clock output enable bit This bit enables or disables continuous serial clock output from the SCK pin. In operating mode 2 (synchronous) in which the serial clock transmission side is selected, setting the CCO bit to "1"...

  • Page 275: Lin-uart Extended Communication Control Register (eccr)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.6 LIN-UART Extended Communication Control Register (ECCR) The LIN-UART extended communication control register (ECCR) is used for the bus idle detection, the synchronous clock setting, and the LIN synch break generation. ■ Register Configuration...

  • Page 276

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers [bit4] SCDE: Serial clock delay enable bit In operating mode 2 in which the serial clock transmission side is selected, if the SCDE bit is set to "1", a delayed serial clock as shown in Figure 14.6-5 is output. The function of outputting delayed serial clock can be used in the Serial Peripheral Interface (SPI).

  • Page 277: Lin-uart Baud Rate Generator Registers 1, 0 (bgr1, Bgr0)

    CHAPTER 14 LIN-UART MB95630H Series 14.7 Registers 14.7.7 LIN-UART Baud Rate Generator Registers 1, 0 (BGR1, BGR0) The LIN-UART baud rate generator registers 1, 0 (BGR1, BGR0) set the division ratio of the serial clock. In addition, the count value in the transmit reload counter is read from this generator.

  • Page 278: Notes On Using Lin-uart

    CHAPTER 14 LIN-UART MB95630H Series 14.8 Notes on Using LIN-UART 14.8 Notes on Using LIN-UART This section provides notes on using the LIN-UART. ■ Notes on Using LIN-UART ● Enabling operation The LIN-UART has the TXE bit and the RXE bit in the LIN-UART serial control register (SCR) to enable transmission and reception respectively.

  • Page 279

    CHAPTER 14 LIN-UART MB95630H Series 14.8 Notes on Using LIN-UART ● Modifying sampling clock edge select bit (ESCR:SCES) With the SCES bit set to "1", executing the LIN-UART software reset is prohibited. • To modify the SCES bit from "0" to "1"...

  • Page 280

    CHAPTER 14 LIN-UART MB95630H Series 14.8 Notes on Using LIN-UART ● Synch break detection In operating mode 3 (LIN mode), when serial input is 11 bits or more in width and becomes "L", the LBD bit in the extended status control register (ESCR) is set to "1" (synch break detected) and the LIN-UART waits for the synch field.

  • Page 281

    CHAPTER 14 LIN-UART MB95630H Series 14.8 Notes on Using LIN-UART Figure 14.8-1 UART Dominant Bus Operation When reception is always enabled (RXE = 1) Framing error Error is Reception is ongoing Next framing Falling edge is occurs cleared regardress of no falling...

  • Page 282

    CHAPTER 14 LIN-UART MB95630H Series 14.8 Notes on Using LIN-UART FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 283: Chapter 15 8/10-bit A/d Converter

    8/10-BIT A/D CONVERTER This chapter describes the functions and operations of the 8/10-bit A/D converter. 15.1 Overview 15.2 Configuration 15.3 Pin 15.4 Interrupt 15.5 Operations and Setting Procedure Example 15.6 Registers 15.7 Notes on Using 8/10-bit A/D Converter MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 284

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.1 Overview 15.1 Overview The 8/10-bit A/D converter is a 10-bit successive approximation type of 8/10-bit A/D converter. It can be started by the software and internal clock, with one input signal selected from multiple analog input pins.

  • Page 285

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.2 Configuration 15.2 Configuration The 8/10-bit A/D converter consists of the following blocks: • Clock selector (input clock selector for starting A/D conversion) • Analog channel selector • Sample-and-hold circuit • Control circuit •...

  • Page 286

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.2 Configuration ● Sample-and-hold circuit This circuit holds input voltage selected by the analog channel selector. By sampling the input voltage and holding it immediately after A/D conversion starts, this circuit prevents A/D conversion from being affected by the fluctuation in input voltage during the conversion (comparison).

  • Page 287

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.3 Pin 15.3 This section describes the pin of the 8/10-bit A/D converter. ■ Pin of 8/10-bit A/D Converter The analog input pin is also used as a general-purpose I/O port. ● AN pin When using the A/D conversion function, input to the AN pin the analog voltage to be converted.

  • Page 288

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.4 Interrupt 15.4 Interrupt The completion of conversion during the operation of the A/D converter is an interrupt source of the 8/10-bit A/D converter. ■ Interrupt During 8/10-bit A/D Converter Operation When A/D conversion is completed, the interrupt request flag bit (ADC1:ADI) is set to "1".

  • Page 289

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.5 Operations and Setting Procedure Example 15.5 Operations and Setting Procedure Example The 8/10-bit A/D converter can activate A/D conversion with the software or activate A/D conversion continuously according to the setting of the EXT bit in the ADC2 register.

  • Page 290

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.5 Operations and Setting Procedure Example ● Continuous activation The settings shown in Figure 15.5-2 are required for continuous activation of the A/D conversion function. Figure 15.5-2 Settings for A/D Conversion Function (Continuous Activation)

  • Page 291

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.5 Operations and Setting Procedure Example ■ Setting Procedure Example Below is an example of procedure for setting the 8/10-bit A/D converter: ● Initial settings 1. Set the input port. (DDR) 2. Set the interrupt level. (ILR*) 3.

  • Page 292

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.6 Registers 15.6 Registers This section describes the registers of the 8/10-bit A/D converter. Table 15.6-1 List of 8/10-bit A/D Converter Registers Register Register name Reference abbreviation ADC1 8/10-bit A/D converter control register 1 15.6.1...

  • Page 293: Bit A/d Converter Control Register 1 (adc1)

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.6 Registers 15.6.1 8/10-bit A/D Converter Control Register 1 (ADC1) The 8/10-bit A/D converter control register 1 (ADC1) is used to enable and disable individual functions of the 8/10-bit A/D converter, select an analog input pin and check the status of the converter.

  • Page 294

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.6 Registers [bit3] ADI: Interrupt request flag bit This bit detects the completion of A/D conversion. When the A/D conversion function is used, the bit is set to "1" immediately after A/D conversion is complete.

  • Page 295: Bit A/d Converter Control Register 2 (adc2)

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.6 Registers 15.6.2 8/10-bit A/D Converter Control Register 2 (ADC2) The 8/10-bit A/D converter control register 2 (ADC2) is used to control different functions of the 8/10-bit A/D converter, select the input clock, and enable and disable interrupts.

  • Page 296

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.6 Registers [bit3] ADIE: Interrupt request enable bit This bit enables or disables outputting interrupts to the interrupt controller. Interrupt requests are output when both this bit and the interrupt request flag bit (ADC1: ADI) have been set to "1".

  • Page 297: Bit A/d Converter Data Register (upper/lower) (addh/addl)

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.6 Registers 15.6.3 8/10-bit A/D Converter Data Register (Upper/Lower) (ADDH/ADDL) The 8/10-bit A/D converter data register (upper/lower) (ADDH/ADDL) store the results of 10-bit A/D conversion during 10-bit A/D conversion. The upper two bits of 10-bit data are stored in the ADDH register and the lower eight bits the ADDL register.

  • Page 298: Notes On Using 8/10-bit A/d Converter

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.7 Notes on Using 8/10-bit A/D Converter 15.7 Notes on Using 8/10-bit A/D Converter This section provides notes on using the 8/10-bit A/D converter. ■ Notes on Using 8/10-bit A/D Converter ● Note on setting the 8/10-bit A/D converter with a program •...

  • Page 299

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.7 Notes on Using 8/10-bit A/D Converter • When setting the A/D converter in software, ensure that the settings satisfy the specifications of "sampling time" and "compare time" of the A/D converter mentioned in the device data sheet.

  • Page 300

    CHAPTER 15 8/10-BIT A/D CONVERTER MB95630H Series 15.7 Notes on Using 8/10-bit A/D Converter FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 301: Chapter 16 Low-voltage Detection Reset Circuit

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT This chapter describes the function and operation of the low-voltage detection reset circuit. 16.1 Overview 16.2 Configuration 16.3 Pins 16.4 Operation 16.5 Register MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 302

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.1 Overview 16.1 Overview The low-voltage detection reset circuit monitors power supply voltage and generates a reset signal if the power supply voltage drops below the low- voltage detection voltage level. ■ Low-voltage Detection Reset Circuit The low-voltage detection reset circuit monitors power supply voltage and generates a reset signal if the power supply voltage drops below the low-voltage detection voltage level.

  • Page 303

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.2 Configuration 16.2 Configuration Figure 16.2-1 is the block diagram of the low-voltage detection reset circuit. ■ Block Diagram of Low-voltage Detection Reset Circuit Figure 16.2-1 Block Diagram of Low-voltage Detection Reset Circuit...

  • Page 304

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.3 Pins 16.3 Pins This section describes the pins of the low-voltage detection reset circuit. ■ Pins of Low-voltage Detection Reset Circuit ● V The low-voltage detection reset circuit monitors the voltage of this pin.

  • Page 305

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.4 Operation 16.4 Operation The low-voltage detection reset circuit generates a reset signal if the power supply voltage falls below the detection voltage. ■ Reset Threshold Voltage In the case of changing the reset threshold voltage in the LVDR register, the new threshold...

  • Page 306

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.5 Register 16.5 Register This section describes the register of low-voltage detection reset circuit. Table 16.5-1 List of Low-voltage Detection Reset Circuit Register Register Register name Reference abbreviation LVDR LVD reset voltage selection ID register 16.5.1...

  • Page 307: Lvd Reset Voltage Selection Id Register (lvdr), Lvd Reset Voltage Selection Id Register (lvdr)

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.5 Register 16.5.1 LVD Reset Voltage Selection ID Register (LVDR) The LVD reset voltage selection ID register (LVDR) selects the reset threshold voltage. ■ Register Configuration Field LVRS7 LVRS6 LVRS5 LVRS4 LVRS3...

  • Page 308

    CHAPTER 16 LOW-VOLTAGE DETECTION RESET CIRCUIT MB95630H Series 16.5 Register FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 309: Chapter 17 Clock Supervisor Counter

    CHAPTER 17 CLOCK SUPERVISOR COUNTER This chapter describes the functions and operations of the clock supervisor counter. 17.1 Overview 17.2 Configuration 17.3 Operations 17.4 Registers 17.5 Notes on Using Clock Supervisor Counter MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 310

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.1 Overview 17.1 Overview The clock supervisor counter checks the external clock frequency to detect the abnormal state of the external clock. ■ Overview of Clock Supervisor Counter The clock supervisor counter checks the external clock frequency to detect the abnormal state of the external clock.

  • Page 311

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.2 Configuration 17.2 Configuration The clock supervisor counter consists of the following blocks: • Control circuit • Clock Monitoring Control Register (CMCR) • Clock Monitoring Data Register (CMDR) • Time-base timer output selector •...

  • Page 312

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.2 Configuration ● Control circuit This block controls the start and stop of the counter, the counter clock source, and the counter enable period based on the settings of the clock monitoring control register (CMCR).

  • Page 313

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.3 Operations 17.3 Operations This section describes the operations of the clock supervisor counter. ■ Clock Supervisor Counter ● Clock Supervisor Counter Operation 1 The clock supervisor counter is first enabled by the software (CMCEN = 1), and then the clock supervisor counter operates with the time-base timer interval selected from eight options by the TBTSEL[2:0] bits.

  • Page 314

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.3 Operations ● Clock Supervisor Counter Operation 3 The counter stops counting if it reaches "255". It cannot count further than "255". Figure 17.3-3 Clock Supervisor Counter Operation 3 Selected time-base timer interval...

  • Page 315

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.3 Operations ■ Table of Time-base Timer Intervals & Clock Supervisor Counter Values Table 17.3-1 shows time-base timer intervals suitable for using different main CR clock frequencies to measure different external clocks. Table 17.3-1 Table of Counter Values in Relation to TBTSEL Settings...

  • Page 316

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.3 Operations Table 17.3-1 is calculated by the following equation: × 1/F (TBTSEL=000) × 1/F (TBTSEL=001) × 1/F (TBTSEL=010) × 1/F × Main/Sub-Oscillation Clock Frequency (TBTSEL=011) × 1/F (TBTSEL=100) × 1/F (TBTSEL=101) × 1/F (TBTSEL=110) ×...

  • Page 317

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.3 Operations ■ Sample Operation Flow Chart of Clock Supervisor Figure 17.3-6 Sample Operation Flow Chart of Clock Supervisor Clock supervision starts Oscillation stabilization wait time elapses In main CR clock mode, wait for the elapse of the...

  • Page 318

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.4 Registers 17.4 Registers This section describes the registers of the clock supervisor counter. Table 17.4-1 List of Clock Supervisor Counter Registers Register Register name Reference abbreviation CMDR Clock monitoring data register 17.4.1...

  • Page 319: Clock Monitoring Data Register (cmdr), Clock Monitoring Data Register (cmdr)

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.4 Registers 17.4.1 Clock Monitoring Data Register (CMDR) The clock monitoring data register (CMDR) is used to read the count value after the clock supervisor counter stops. The software can check whether the external clock frequency is correct or not according to the content of this register.

  • Page 320: Clock Monitoring Control Register (cmcr), Clock Monitoring Control Register (cmcr)

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.4 Registers 17.4.2 Clock Monitoring Control Register (CMCR) The clock monitoring control register (CMCR) is used to select the counter source clock, select a time-base timer interval as the counter enable period, start the counter and check whether the counter is running or not.

  • Page 321

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.4 Registers [bit0] CMCEN: Counter enable bit This bit enables or disables the clock supervisor counter. Writing "0" to this bit stops the counter and clears the CMDR register to "0b00000000". Writing "1" to this bit enables the counter. The counter starts counting when detecting the rising edge of the time-base timer interval.

  • Page 322: Notes On Using Clock Supervisor Counter

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.5 Notes on Using Clock Supervisor Counter 17.5 Notes on Using Clock Supervisor Counter This section provides notes on using the clock supervisor counter. ■ Notes on Using Clock Supervisor Counter ● Restrictions •...

  • Page 323

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.5 Notes on Using Clock Supervisor Counter ● If the external clock stops while the clock supervisor counter is operating, and it restarts after the second rising edge of the time-base timer interval selected, CMCEN is set to "0"...

  • Page 324

    CHAPTER 17 CLOCK SUPERVISOR COUNTER MB95630H Series 17.5 Notes on Using Clock Supervisor Counter FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 325: Chapter 18 8/16-bit Ppg

    8/16-BIT PPG This chapter describes the functions and operations of the 8/16-bit PPG. 18.1 Overview 18.2 Configuration 18.3 Channel 18.4 Pins 18.5 Interrupt 18.6 Operations and Setting Procedure Example 18.7 Registers 18.8 Notes on Using 8/16-bit PPG MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 326

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.1 Overview 18.1 Overview The 8/16-bit PPG is an 8-bit reload timer module that uses pulse output control based on timer operation to perform PPG output. The 8/16-bit PPG also operates in cascade (8 bits + 8 bits) as 16-bit PPG.

  • Page 327

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.2 Configuration 18.2 Configuration This section shows the block diagram of the 8/16-bit PPG. ■ Block Diagram of 8/16-bit PPG Figure 18.2-1 shows the block diagram of the 8/16-bit PPG. Figure 18.2-1 Block Diagram of 8/16-bit PPG...

  • Page 328

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.2 Configuration ● Counter clock selector The clock for the countdown of 8-bit downcounter is selected from eight types of internal count clocks. ● 8-bit downcounter It counts down with the count clock selected with the count clock selector.

  • Page 329

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.3 Channel 18.3 Channel This section describes the channel of the 8/16-bit PPG. ■ Channel of 8/16-bit PPG The 8/16-bit PPG consists of 8-bit PPG timer n0 and 8-bit PPG timer n1. They can be used respectively as two 8-bit PPGs or as a single 16-bit PPG.

  • Page 330

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.4 Pins 18.4 Pins This section describes the pins of the 8/16-bit PPG. ■ Pins of 8/16-bit PPG ● PPGn0 pin and PPGn1 pin These pins function both as general-purpose I/O ports and 8/16-bit PPG outputs.

  • Page 331

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.5 Interrupt 18.5 Interrupt The 8/16-bit PPG outputs an interrupt request when a counter borrow is detected. ■ Interrupt of 8/16-bit PPG Table 18.5-1 shows the interrupt control bits and interrupt sources of the 8/16-bit PPG.

  • Page 332

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example 18.6 Operations and Setting Procedure Example This section describes the operations of the 8/16-bit PPG. The 8/16-bit PPG has the following three operating modes: • 8-bit PPG independent mode •...

  • Page 333: Bit Ppg Independent Mode

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example 18.6.1 8-bit PPG Independent Mode In this mode, the 8/16-bit PPG operates as two channels (PPG timer n0 and PPG timer n1) of the 8-bit PPG. ■ Setting 8-bit PPG Independent Mode The 8/16-bit PPG requires the register settings shown in Figure 18.6-1 to operate in 8-bit PPG...

  • Page 334

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example Figure 18.6-2 Operation of 8-bit PPG Independent Mode Count clock (Cycle T) (Counter start) Stop Cycle setting (PPS) Duty setting (PDS) PPG timer n0 counter value Downcounter value matches...

  • Page 335: Bit Prescaler + 8-bit Ppg Mode

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example 18.6.2 8-bit Prescaler + 8-bit PPG Mode In this mode, the rising and falling edge detection pulses from the PPG timer n1 output can be used as the count clock of the PPG timer n0 downcounter to allow variable-cycle 8-bit PPG output from PPG timer n0.

  • Page 336

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example reversed and the signal is output to the PPGn1 pin. • When the PPG timer n0 (ch. n) downcounter operation enable bit (PEN00) is set to "1", the...

  • Page 337: Bit Ppg Mode

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example 18.6.3 16-bit PPG Mode In this mode, the 8/16-bit PPG can operate as a 16-bit PPG when PPG timer n1 and PPG timer n0 are assigned to the upper and lower bits respectively.

  • Page 338

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example is the value of duty setting is output, the PPGn0 pin is set to "L". If the output level reverse bit (REV00) is "0", the signal is output to the PPGn0 pin with the polarity unchanged. If it is set to "1", the polarity is reversed and the signal is output to the PPGn0 pin.

  • Page 339

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.6 Operations and Setting Procedure Example ■ Setting Procedure Example Below is an example of procedure for setting the 8/16-bit PPG ch. n. ● Initial setup 1. Set the port output. (DDR) 2. Set the interrupt level. (ILR*) 3.

  • Page 340

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7 Registers This section describes the registers of the 8/16-bit PPG. Table 18.7-1 List of 8/16-bit PPG Registers Register Register name Reference abbreviation PCn1 8/16-bit PPG timer n1 control register 18.7.1 PCn0 8/16-bit PPG timer n0 control register 18.7.2...

  • Page 341: Bit Ppg Timer N1 Control Register (pcn1)

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7.1 8/16-bit PPG timer n1 Control Register (PCn1) The 8/16-bit PPG timer n1 control register (PCn1) sets the operating conditions for PPG timer n1. ■ Register Configuration Field — — PIE1 PUF1...

  • Page 342

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers [bit2:0] CKS1[2:0]: Operating clock select bits These bits select the operating clock for 8-bit downcounter of the PPG timer n1. The operating clock is generated from the prescaler. For details, see "3.9 Operation of Prescaler".

  • Page 343: Bit Ppg Timer N0 Control Register (pcn0)

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7.2 8/16-bit PPG timer n0 Control Register (PCn0) The 8/16-bit PPG timer n0 control register (PCn0) sets the operating conditions and the operation mode for PPG timer n0. ■ Register Configuration Field...

  • Page 344

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers [bit3] POEN0: Output enable bit This bit enables or disables the PPG timer n0 pin output. In 16-bit PPG mode, since the 8/16-bit PPG outputs pulse wave through the PPG timer n0 pin, this bit controls the 8/16-bit PPG output.

  • Page 345: Bit Ppg Timer N1/n0 Cycle Setup Buffer Register (ppsn1/ppsn0)

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7.3 8/16-bit PPG timer n1/n0 Cycle Setup Buffer Register (PPSn1/PPSn0) The 8/16-bit PPG timer n1/n0 cycle setup buffer register (PPSn1/PPSn0) sets the PPG output cycle. ■ Register Configuration PPSn1 Field Attribute Initial value...

  • Page 346: Bit Ppg Timer N1/n0 Duty Setup Buffer Register (pdsn1/pdsn0)

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7.4 8/16-bit PPG timer n1/n0 Duty Setup Buffer Register (PDSn1/PDSn0) The 8/16-bit PPG timer n1/n0 duty setup buffer register (PDSn1/PDSn0) sets the duty of the PPG output. ■ Register Configuration PDSn1 Field...

  • Page 347: Bit Ppg Start Register (ppgs)

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7.5 8/16-bit PPG Start Register (PPGS) The 8/16-bit PPG start register (PPGS) starts or stops the downcounter. The operation enable bit of each channel is assigned to the PPGS register, allowing simultaneous activation of the PPG channels.

  • Page 348

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers [bit1] PEN01: PPG timer 01 (ch. 0) downcounter operation enable bit This bit enables or stops the downcounter operation of PPG timer 01 (ch. 0). bit1 Details Writing "0" Stops the downcounter operation of PPG timer 01 (ch. 0).

  • Page 349: Bit Ppg Output Reverse Register (revc)

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers 18.7.6 8/16-bit PPG Output Reverse Register (REVC) The 8/16-bit PPG output reverse register (REVC) reverses the PPG output including the initial level. ■ Register Configuration Field — — REV21* REV20* REV11* REV10*...

  • Page 350

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.7 Registers [bit1] REV01: PPG timer 01 (ch. 0) output level reverse bit This bit selects the output level of PPG timer 01 (ch. 0). bit1 Details Writing "0" Selects normal polarity. Writing "1"...

  • Page 351: Notes On Using 8/16-bit Ppg

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.8 Notes on Using 8/16-bit PPG 18.8 Notes on Using 8/16-bit PPG This section provides notes on using the 8/16-bit PPG. ■ Notes on Using 8/16-bit PPG ● Note on operation Depending on the timing between the activation of PPG and count clock, an error may occur in the first cycle of the PPG output immediately after the activation.

  • Page 352

    CHAPTER 18 8/16-BIT PPG MB95630H Series 18.8 Notes on Using 8/16-bit PPG FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 353: Chapter 19 16-bit Ppg Timer

    This chapter describes the functions and operations of the 16-bit PPG timer. 19.1 Overview 19.2 Configuration 19.3 Channel 19.4 Pins 19.5 Interrupts 19.6 Operations and Setting Procedure Example 19.7 Registers 19.8 Notes on Using 16-bit PPG Timer MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 354

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.1 Overview 19.1 Overview The 16-bit PPG timer can generate a PWM (Pulse Width Modulation) output or one-shot (square wave) output, and the period and duty of the output waveform can be changed by software freely. The timer can also generate an interrupt when a start trigger occurs or on the rising or falling edge of the output waveform.

  • Page 355

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.2 Configuration 19.2 Configuration This section describes the configuration of the 16-bit PPG timer. The number of pins and that of channels of the 16-bit PPG vary among products. For details, refer to the device data sheet.

  • Page 356

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.2 Configuration ● Comparator circuit The output is kept "H" until the value of 16-bit downcounter is corresponding to the value of the 16-bit PPG duty setting buffer register from the value of 16-bit PPG cycle setting buffer register.

  • Page 357

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.3 Channel 19.3 Channel This section describes the channel of the 16-bit PPG timer. ■ Channel of 16-bit PPG Timer Table 19.3-1 and Table 19.3-2 show the pins and registers on a channel of the 16-bit PPG timer respectively.

  • Page 358

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.4 Pins 19.4 Pins This section describes the pins of the 16-bit PPG timer. ■ Pins of 16-bit PPG Timer The pins of the 16-bit PPG timer are the PPGn pin and TRGn pin.

  • Page 359

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.5 Interrupts 19.5 Interrupts The 16-bit PPG timer can generate interrupt requests in the following cases: • When a trigger or counter borrow occurs • When a rising edge of PPG is generated in normal polarity •...

  • Page 360

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.6 Operations and Setting Procedure Example 19.6 Operations and Setting Procedure Example The 16-bit PPG timer can operate in PWM mode or one-shot mode. In addition, a retrigger function can be used in the 16-bit PPG timer.

  • Page 361

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.6 Operations and Setting Procedure Example ● Invalidating the retrigger (RTRG bit in PCNTHn register = 0) Figure 19.6-1 When Retrigger Is Invalid in PWM Mode 16-bit downcounter value Time Rising edge detected...

  • Page 362

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.6 Operations and Setting Procedure Example ■ One-shot Mode (MDSE Bit in PCNTHn Register = 1) One-shot operation mode can be used to output a single pulse with a specified width when a valid trigger input occurs.

  • Page 363

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.6 Operations and Setting Procedure Example ■ Hardware Trigger "Hardware trigger" refers to PPG activation by signal input to the TRGn input pin. When EGS1 and EGS0 are set to "0b11" and the hardware trigger is used with TRGn input, PPG starts operation on a rising edge and halts the operation upon the detection of a falling edge.

  • Page 364

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers 19.7 Registers This section describes the registers of the 16-bit PPG timer. Table 19.7-1 List of 16-bit PPG Timer Registers Register Register name Reference abbreviation PDCRHn 16-bit PPG downcounter register (upper) 19.7.1...

  • Page 365: Bit Ppg Downcounter Register (upper/lower) (pdcrhn/pdcrln)

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers 19.7.1 16-bit PPG Downcounter Register (Upper/Lower) (PDCRHn/PDCRLn) The 16-bit PPG downcounter register (upper) (PDCRHn) and the 16-bit PPG downcounter register (lower) (PDCRLn) form a 16-bit register that is used to read the count value from the 16-bit PPG downcounter.

  • Page 366: Bit Ppg Cycle Setting Buffer Register (upper/ Lower) (pcsrhn/pcsrln)

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers 19.7.2 16-bit PPG Cycle Setting Buffer Register (Upper/ Lower) (PCSRHn/PCSRLn) The 16-bit PPG cycle setting buffer registers are used to set the cycle for the output pulses generated by the PPG.

  • Page 367: Bit Ppg Duty Setting Buffer Register (upper/lower) (pduthn/pdutln)

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers 19.7.3 16-bit PPG Duty Setting Buffer Register (Upper/Lower) (PDUTHn/PDUTLn) The 16-bit PPG duty setting buffer registers control the duty ratio for the output pulses generated by the PPG. ■ Register Configuration...

  • Page 368: Bit Ppg Status Control Register (upper) (pcnthn)

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers 19.7.4 16-bit PPG Status Control Register (Upper) (PCNTHn) The 16-bit PPG status control register (upper) enables or disables the 16-bit PPG timer, and controls the software trigger, operating mode, operating clock and output mask.

  • Page 369

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers [bit4] RTRG: Software retrigger enable bit This bit enables or disables using the software retrigger function while the 16-bit PPG timer is in operation. bit4 Details Writing "0" Disables using the software retrigger function while the 16-bit PPG timer is in operation.

  • Page 370: Bit Ppg Status Control Register (lower) (pcntln)

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers 19.7.5 16-bit PPG Status Control Register (Lower) (PCNTLn) The 16-bit PPG status control register (lower) controls the hardware trigger, interrupt, output, and output polarity of the 16-bit PPG timer. ■ Register Configuration...

  • Page 371

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.7 Registers [bit3:2] IRS[1:0]: Interrupt type select bit These bits select the interrupt source type for the 16-bit PPG timer. bit3:2 Details Writing "00" Trigger by input, software trigger, or retrigger Writing "01"...

  • Page 372: Notes On Using 16-bit Ppg Timer

    CHAPTER 19 16-BIT PPG TIMER MB95630H Series 19.8 Notes on Using 16-bit PPG Timer 19.8 Notes on Using 16-bit PPG Timer This section provides notes on using the 16-bit PPG timer. ■ Notes on Using 16-bit PPG Timer ● Notes on setting the program Do not use the retrigger if the same values are set for the cycle and duty.

  • Page 373: Chapter 20 16-bit Reload Timer

    This chapter describes the functions and operations of the 16-bit reload timer. 20.1 Overview 20.2 Configuration 20.3 Channel 20.4 Pins 20.5 Interrupt 20.6 Operations and Setting Procedure Example 20.7 Registers 20.8 Notes on Using 16-bit Reload Timer MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 374

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.1 Overview 20.1 Overview The 16-bit reload timer has two counter operating modes in each of the two clock modes. The 16-bit reload timer can be used as an interval timer by generating an interrupt when an underflow occurs in the timer.

  • Page 375

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.1 Overview ■ Counter Operating Mode ● Reload mode When an underflow occurs in the 16-bit downcounter ("0x0000" → "0xFFFF"), the value of the 16-bit reload timer reload register (TMRLRHn/TMRLRLn) is loaded to the 16-bit downcounter and the 16-bit reload timer continues counting.

  • Page 376

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.2 Configuration 20.2 Configuration The 16-bit reload timer consists of the following blocks: • Count clock generation circuit • Reload control circuit • Output control circuit • Operation control circuit • 16-bit reload timer timer register (TMRHn, TMRLn) •...

  • Page 377

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.2 Configuration ● Count clock generation circuit The count clock for the 16-bit reload timer is generated from the internal clock or TIn pin input signal. ● Reload control circuit This circuit controls reload operation when the timer is started or an underflow occurs.

  • Page 378

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.3 Channel 20.3 Channel This section describes the channel of the 16-bit reload timer. ■ Channel of 16-bit Reload Timer Table 20.3-1 and Table 20.3-2 show the pins and registers on a channel of the 16-bit reload timer respectively.

  • Page 379

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.4 Pins 20.4 Pins This section describes the pins of the 16-bit reload timer and shows the block diagram of these pins. ■ Pins of 16-bit Reload Timer The pins of the 16-bit reload timer are namely the TIn and TOn pins.

  • Page 380

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.5 Interrupt 20.5 Interrupt The 16-bit reload timer outputs an interrupt request when an underflow occurs on the 16-bit downcounter. ■ Interrupt of 16-bit Reload Timer Table 20.5-1 shows the interrupt control bit and interrupt source of the 16-bit reload timer.

  • Page 381

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example 20.6 Operations and Setting Procedure Example This section describes the operating status of the 16-bit reload timer counter. ■ Operating Status of Counter The counter status is determined by the value of the count enable bit (CNTE) in the 16-bit reload timer control status register (lower) (TMCSRLn) and the internal signal start trigger wait signal (WAIT).

  • Page 382

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example ■ Setting Procedure Example Below is an example of procedure for setting the 16-bit reload timer. ● Initial setup 1. Set the interrupt level. (ILR*) 2. Set the reload value. (TMRHn/TMRLn) 3.

  • Page 383: Internal Clock Mode

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example 20.6.1 Internal Clock Mode In this mode, the 16-bit downcounter counts down while being synchronized with the internal count clock, and outputs an interrupt request to the interrupt controller every time an underflow occurs ("0x0000"...

  • Page 384

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example ● Software trigger operation When the count enable bit (CNTE) is set to "1", setting "1" to the software trigger bit (TRG) starts counting. Figure 20.6-3 shows the software trigger operation in reload mode.

  • Page 385

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example Figure 20.6-5 Count Operation in Reload Mode (External Gate Input Operation) Count clock 0000 Counter Reload data Reload data Data load signal UF bit CNTE bit TRG bit...

  • Page 386

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example ● External trigger input The count starts when the count enable bit (CNTE) is "1" and the valid edge of trigger input (rising, falling, or both edges) specified by the operating mode select bits (MOD[2:0]) is input to the TIn pin.

  • Page 387: Event Count Mode

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example 20.6.2 Event Count Mode In this mode, the 16-bit downcounter counts down each time the valid edge is detected on the pulses input to the TIn pin, and an interrupt request is output to the interrupt controller when an underflow occurs ("0x0000"...

  • Page 388

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.6 Operations and Setting Procedure Example Figure 20.6-10 Count Operation in Reload Mode (Event Count Mode) TIn pin 0000 0000 0000 Counter Reload data Reload data Reload data Reload data Data load signal...

  • Page 389

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers 20.7 Registers This section describes the registers of the 16-bit reload timer. Table 20.7-1 List of 16-bit Reload Timer Registers Register Register name Reference abbreviation TMCSRHn 16-bit reload timer control status register (upper) 20.7.1...

  • Page 390: Bit Reload Timer Control Status Register (upper) (tmcsrhn)

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers 20.7.1 16-bit Reload Timer Control Status Register (Upper) (TMCSRHn) The 16-bit reload timer control status register (upper) (TMCSRHn) sets the operating mode and operating conditions of the 16-bit reload timer. ■ Register Configuration Field —...

  • Page 391

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers [bit2:0] MOD[2:0]: Operating mode select bits These bits set the operating conditions of the 16-bit reload timer. • Internal clock mode (CSL[2:0] = any value between 0b000 and 0b110 inclusive) Select the input pin function with the MOD2 bit.

  • Page 392: Bit Reload Timer Control Status Register (lower) (tmcsrln)

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers 20.7.2 16-bit Reload Timer Control Status Register (Lower) (TMCSRLn) The 16-bit reload timer control status register (lower) (TMCSRLn) sets the operating conditions of the 16-bit reload timer, enables or disables counting, controls interrupts, and checks the interrupt request status.

  • Page 393

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers [bit3] INTE: Underflow interrupt request enable bit This bit enables or disables the underflow interrupt. bit3 Details Writing "0" Disables the underflow interrupt. Writing "1" Enables the underflow interrupt. [bit2] UF: Underflow interrupt request flag bit This bit indicates whether an underflow has occurred in the 16-bit reload timer.

  • Page 394: Bit Reload Timer Timer Register (upper/lower) (tmrhn/tmrln)

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers 20.7.3 16-bit Reload Timer Timer Register (Upper/Lower) (TMRHn/TMRLn) The 16-bit reload timer timer register (upper/lower) (TMRHn/TMRLn) reads the count value of the 16-bit downcounter. ■ Register Configuration TMRHn Field Attribute Initial value...

  • Page 395: Bit Reload Timer Reload Register (upper/lower) (tmrlrhn/tmrlrln)

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.7 Registers 20.7.4 16-bit Reload Timer Reload Register (Upper/Lower) (TMRLRHn/TMRLRLn) The 16-bit reload timer reload register (upper/lower) (TMRLRHn/TMRLRLn) sets the reload value for the 16-bit downcounter. The value written to this register is reloaded to the 16-bit downcounter for downcounting.

  • Page 396: Notes On Using 16-bit Reload Timer

    CHAPTER 20 16-BIT RELOAD TIMER MB95630H Series 20.8 Notes on Using 16-bit Reload Timer 20.8 Notes on Using 16-bit Reload Timer This section provides notes on using the 16-bit reload timer. ■ Notes on Using 16-bit Reload Timer ● Notes on setting the program •...

  • Page 397: Chapter 21 Multi-pulse Generator

    This chapter describes the specifications and operations of the multi-pulse generator. 21.1 Overview 21.2 Block Diagram 21.3 Pins 21.4 Interrupts 21.5 Operations 21.6 Registers 21.7 Notes on Using Multi-pulse Generator 21.8 Sample Program for Multi-pulse Generator MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 398

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.1 Overview 21.1 Overview The multi-pulse generator consists of a 16-bit PPG timer, a 16-bit reload timer and a waveform sequencer. By using the waveform sequencer, 16-bit PPG timer output signal can be directed to multi-pulse generator output (OPT5 to OPT0) according to the input signal of the multi-pulse generator (SNI2 to SNI0).

  • Page 399

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.1 Overview • In the waveform sequencer, there is a 16-bit timer that can be used to measure the speed of the motor and disable the OPT output in case of position detect missing.

  • Page 400

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.1 Overview Figure 21.1-2 PPG Falling Edge Synchronization Asynchronous State Change WTS[1:0] = 0b00 Glitch Synchronous State Change WTS[1:0] = 0b10 OP5’ OP4’ The sequencer changes its state (e.g. due to a reload timer underflow).

  • Page 401: Block Diagram

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram 21.2 Block Diagram Figure 21.2-1 shows the block diagram of the multi-pulse generator and Figure 21.2-2 the block diagram of the waveform sequencer. ■ Block Diagram of Multi-pulse Generator Figure 21.2-1 Block Diagram of Multi-pulse Generator...

  • Page 402

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ● 16-bit reload timer The 16-bit reload timer is used to act as the interval timer for the waveform sequencer. Details of the 16-bit reload timer are described in "CHAPTER 20 16-BIT RELOAD TIMER".

  • Page 403

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ● 16-bit timer The 16-bit timer is used to act as an interval timer for motor speed checking and abnormal detection timer for controlling a DC sensorless motor. The detail is shown in Figure 21.2-3.

  • Page 404

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ● 16-bit MPG output control register (upper) (OPCUR) and 16-bit MPG output control register (lower) (OPCLR) The 16-bit MPG output control register (upper) (OPCUR) and the 16-bit MPG output control register (lower) (OPCLR) are registers that enable the write timing interrupt and flag, position detect interrupt and flag, set the data transfer method, and control the output of the OPT5 to OPT0 pins and the input of the DTTI pin.

  • Page 405

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ■ Block Diagram of 16-bit Timer Figure 21.2-3 Block Diagram of 16-bit Timer Compare clear interrupt (CCIRT) MCLK TCSR TCLR ICLR ICRE MODE TMEN CLK2 CLK1 CLK0 Prescaler Clock 16-bit up counter...

  • Page 406

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ● 16-bit MPG timer buffer register (upper) (TMBUR) and 16-bit MPG timer buffer register (lower) (TMBLR) The 16-bit MPG timer buffer register (upper) (TMBUR) and the 16-bit MPG timer buffer register (lower) (TMBLR) are used store the value of the 16-bit up counter when a write timing interrupt or position detect interrupt occurs.

  • Page 407

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ● Selector 1 The selector 1 is used to select from among Write both OPDBRHx and OPDBRLx or TOUT of 16-bit reload timer or WTIN1 of position detect circuit to generate the Write Timing signal (WTO).

  • Page 408

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.2 Block Diagram ■ Block Diagram of Position Detection Circuit Figure 21.2-5 Block Diagram of Position Detection Circuit RDA2 RDA1 RDA0 COMPARISON CIRCUIT NOISE EDGE FILTER DETECTION SNI0 CIRCUIT CIRCUIT 0 SEE0 CPE1 CPE0...

  • Page 409

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.3 Pins 21.3 Pins This section describes the pins of the multi-pulse generator. ■ Pins of Multi-pulse Generator The multi-pulse generator uses OPT0 to OPT5, SNI0 to SNI2, DTTI and TI1. ● OPT0 to OPT5 pins The OPT0 to OPT5 pins function as waveform output pins for the multi-pulse generator.

  • Page 410

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.4 Interrupts 21.4 Interrupts The multi-pulse generator can generate an interrupt request due to the following sources: • Write timing output is generated by the data write control unit • Any valid position detection input is detected •...

  • Page 411

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.4 Interrupts generated by either the compare match of the level of the position input (SNI2 to SNI0) with the RDA[2:0] bits in the 16-bit MPG output data register (upper) (OPDUR), or a edge detected of the position input (SNI2 to SNI0) with one of 3 different kinds of edge setting.

  • Page 412

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5 Operations The operations of the multi-pulse generator will be described in the following sections. According to the settings of the OPx1 and OPx0 bits in the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR), the OPTx pin outputs the corresponding kind of waveforms ("H"...

  • Page 413: Bit Mpg Output Data Register (upper/lower) (opdur/opdlr)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ 16-bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR) The content of the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) is sent from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHB and OPDBRLB - OPDBRH0 and OPDBRL0) according to the write timing signal (WTO) generated by the data write control unit, and the OPTx output waveform is updated.

  • Page 414: Operation Of Position Detection

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.1 Operation of Position Detection This section describes the operation of the Position Detection Circuit. When the effective position is detected, a Data Write Timing Output (WTIN1) will be generated to the data write control unit and a Position Detect Interrupt is generated if the OPCLR:PDIE is set to "1".

  • Page 415

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Both Edges Detection and SNIx/RDAx Comparison Timing Diagram (CMPE = Figure 21.5-4 Both Edges Detection and SNIx/RDAx Comparison Timing Diagram (CMPE = 1) CMPE CPE1, 0b11 CPE0 RDA[2:0] 0b010 0b110 0b001...

  • Page 416: Operation Of Data Write Control Unit

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.2 Operation of Data Write Control Unit The data write control unit is used to generate the write timing output (WTO) for transferring data from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx) to 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR).

  • Page 417

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ OPDUR and OPDLR Write Timing Diagram (OPS[2:0] = 0b000) Figure 21.5-6 OPDUR and OPDLR Write Timing Diagram (OPS[2:0] = 0b000) OPS[2:0] 0b000 RDA[2:0] 0b101 0b001 (OPDUR) ODBR0W ODBR1W OPDBRL0[0] OPDBRL1[0] OP00 ■...

  • Page 418

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Signal Flow Diagram for Position Detection by Setting OPS[2:0] = 0b010 or 0b110 Figure 21.5-8 Signal Flow Diagram for Position Detection (OPS[2:0] = 0b010 or 0b110) TIN0O TIN0 16-BIT RELOAD TIMER...

  • Page 419

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Signal Flow Diagram for Reload Timer or Position Detection by Setting OPS[2:0] = 0b100 or 0b101 Figure 21.5-10 Signal Flow Diagram for Reload Timer or Position Detect (OPS[2:0] = 0b100 or...

  • Page 420: Operation Of 16-bit Mpg Output Data Buffer Register (upper/lower Opdbrhx/opdbrlx)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.3 Operation of 16-bit MPG Output Data Buffer Register (Upper/Lower) (OPDBRHx/OPDBRLx) The 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx) are composed of 12 pairs of registers. By loading different OPDBRHx and...

  • Page 421

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations Setting the 16-bit MPG output data buffer register 0 (upper/lower) (OPDBRH0/OPDBRL0) (No. 0) as shown in Table 21.5-3 initializes the value of the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR). The following sequence begins to operate according to the write timing generated: No.

  • Page 422: Operation Of Data Transfer Of 16-bit Mpg Output Data Register (upper/lower)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4 Operation of Data Transfer of 16-bit MPG Output Data Register (Upper/Lower) Eight methods can be used to transfer data from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx) to the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) automatically, which are described in the following section.

  • Page 423

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations Figure 21.5-12 Structure between OPDBRHx, OPDBRLx and OPDUR, OPDLR OPDBRH0, OPDBRL0 OPDBRH1, OPDBRL1 OPDBRH2, OPDBRL2 OPDBRH3, OPDBRL3 OPDBRH4, OPDBRL4 TO OUTPUT OPDBRH5, OPDBRL5 OPDUR, 12 TO 1 SELECTOR CONTROL OPDLR OPDBRH6, OPDBRL6...

  • Page 424: At Opdbrh0 And Opdbrl0 Write

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.1 At OPDBRH0 and OPDBRL0 Write The timing change of the output pin OPTx, which is triggered by OPDBRH0 and OPDBRL0 write, is shown in Figure 21.5-13. ■ Timing Generated by OPDBRH0 and OPDBRL0 Write (OPS[2:0] = 0b000)

  • Page 425: At 16-bit Reload Timer Underflow

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.2 At 16-bit Reload Timer Underflow The timing change of the output pin OPTx, which is triggered by the 16-bit reload timer underflow, is shown in Figure 21.5-14 and Figure 21.5-15. ■ Timing Generated by Reload Timer Underflow Figure 21.5-14 Timing Generated by Reload Timer Underflow...

  • Page 426

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations The data transfer from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/ OPDBRLx) specified by the BNKF bit and the RDA[2:0] bits to the 16-bit MPG output data register (upper) (OPDUR) is updated automatically whenever a 16-bit reload timer underflow is generated as shown in Figure 21.5-15.

  • Page 427: At Position Detection

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.3 At Position Detection The output timing change, which is triggered by the input pin SNIx for the position detection, is shown in Figure 21.5-16 and Figure 21.5-17. ■ Timing Generated by Position Detection Figure 21.5-16 Timing Generated by Position Detection...

  • Page 428

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations The comparisons between the SNI2 pin and the RDA2 bit, the SNI1 pin and the RDA1 bit, the SNI0 pin and the RDA0 bit are done for each position detection. The OPTx output waveform is updated according to the effective edge input to pin SNIx as shown in Figure 21.5-17.

  • Page 429: At Position Detection And Timer Underflow

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.4 At Position Detection and Timer Underflow The output timing change of the operation of the Position Detection and Reload Timer underflow is shown in Figure 21.5-18 and Figure 21.5-19. ■ Timing Generated by Position Detection and Timer Underflow Figure 21.5-18 Timing Generated by Position Detection and Timer Underflow...

  • Page 430

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations The comparison for the position detection is done in pair for each SNIx pin and RDAx bit (SNI2 and RDA2, SNI1 and RDA1, SNI0 and RDA0), a comparison match starts the 16-bit reload timer.

  • Page 431

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Timing Generated by Position Detection and Timer Underflow (OPS[2:0] = 0b011) Figure 21.5-19 Timing Generated by Position Detection and Timer Underflow (OPS[2:0] = 0b011) SNI2 SNI1 SNI0 TIN0O (TIN) Reload timer...

  • Page 432: At Position Detection Or Timer Underflow

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.5 At Position Detection or Timer Underflow The output timing changes of the operation of the Position Detection or Reload Timer underflow are shown in Figure 21.5-20 and Figure 21.5-21. This operation mode is selected by setting the OPS[2:0] = 0b100.

  • Page 433

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Timing Generated by Position Detection or Timer Underflow (OPS[2:0] = 0b100) Figure 21.5-21 Timing Generated by Position Detection or Timer Underflow (OPS[2:0] = 0b100) SNI2 SNI1 SNI0 WTIN1 Reload Timer Counter...

  • Page 434: At One-shot Position Detection

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.6 At One-shot Position Detection The output timing change, which is triggered by the input pin SNIx for the one- shot position detection, is shown in Figure 21.5-22. ■ When One-shot Position Detection...

  • Page 435: When One-shot Position Detection And Reload Timer Underflow

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.7 When One-shot Position Detection and Reload Timer Underflow The output timing change of the operation of the one-shot position detection and reload timer underflow is shown in Figure 21.5-23. ■ When One-shot Position Detection and Reload Timer Underflow...

  • Page 436: When One-shot Position Detection Or Reload Timer Underflow

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.4.8 When One-shot Position Detection or Reload Timer Underflow The output timing change of the operation of the one-shot position detection or reload timer underflow is shown in Figure 21.5-24. This operation mode is selected by setting the OPS[2:0] = 0b101.

  • Page 437: Operation Of Dtti Input Control

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.5 Operation of DTTI Input Control This section describes the operation of the DTTI input control circuit. ■ Operation of DTTI Input Control The DTTI circuit controls the output of the value of PDRx (port x data register) to the pin OPTx which is multiplexed with the port x where OPTx is enable by setting OPEx = 1.

  • Page 438

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ DTTI Circuit Timing Diagram (D[1:0] = 0b00) Figure 21.5-26 DTTI Circuit Timing Diagram (D[1:0] = 0b00) MCLK DTTI DTIE NRSL DTIF* DTISP DTTI DTIE NRSL DTIF* DTISP 4 Cycles * DTIF is cleared by writing “0” to it.

  • Page 439

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Relationship between DTTI and OPTx Output Table 21.5-4 Relationship between DTTI and OPTx Output NRSL DTIE DTTI Function DTTI has no effect on OPTx. (Initial value) DTTI takes effect. Noise filter is not enabled. An "L" input at DTTI pin triggers the output of the inactive level set in PDRx.

  • Page 440: Operation Of Noise Cancellation Function

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.6 Operation of Noise Cancellation Function This section describes the noise cancellation function for the SNIx and DTTI pins. ■ Operation of Noise Cancellation Function ● DTTI Pin Noise Cancellation Function When the NRSL bit in the 16-bit MPG output control register (upper) (OPCUR) is set to "1", the noise cancellation function for DTTI pin input can be used.

  • Page 441: Operation Of 16-bit Timer

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations 21.5.7 Operation of 16-bit Timer The 16-bit timer has a buffer and compare clear function, which is used for motor speed checking and abnormal detection timeout. The 16-bit timer starts counting up from counter value "0x0000" after a reset has been completed and counting enable bit is set.

  • Page 442

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations Figure 21.5-27 Clearing the Counter by an Overflow Counter value Overflow 0xFFFF 0xBFFF 0x7FFF 0x3FFF 0x0000 Time Reset Interrupt Figure 21.5-28 Clearing the Counter upon a Match with Compare Clear Register Counter value...

  • Page 443

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ 16-bit Timer Timing The 16-bit timer increases its value at timing according to the prescaler clock and counts up at a rising edge. Note: Before the prescaler clock is changed, the Timer Counter should be disabled first by setting the TMEN bit to "0".

  • Page 444

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ 16-bit Timer Buffer Operation Timing Diagram Figure 21.5-31 16-bit Timer Buffer Operation Timing Diagram CPU clock Counter value 0x0000 0x0001 0x0002 0x0000 0x0001 0x0002 Timer buffer 0xXXXX 0x0002 MODE 0 or 1...

  • Page 445

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.5 Operations ■ Using 16-bit Timer of Multi-pulse Generator The timer is reset when write timing or position detection interrupt flag is set, which is selectable by the MODE bit in the 16-bit MPG timer control status register (TCSR).

  • Page 446

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6 Registers This section describes the registers of the multi-pulse generator. Table 21.6-1 List of Multi-pulse Generator Registers Register Register name Reference abbreviation OPCUR 16-bit MPG output control register (upper) 21.6.1 OPCLR 16-bit MPG output control register (lower) 21.6.2...

  • Page 447: Bit Mpg Output Control Register (upper) (opcur), Bit Mpg Output Control Register (upper)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.1 16-bit MPG Output Control Register (Upper) (OPCUR) The 16-bit MPG output control register (upper) (OPCUR) controls the write timing interrupt, the data transfer method and the DTTI pin. ■ Register Configuration...

  • Page 448

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit4:2] OPS[2:0]: Data transfer method select bits These bits control the output timing of OPT5 to OPT0 pins and select the write timing control operation mode. Data is transferred from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx) to the 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) at the write timing controlled by the selected operation mode.

  • Page 449: Bit Mpg Output Control Register (lower) (opclr), Bit Mpg Output Control Register (lower)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.2 16-bit MPG Output Control Register (Lower) (OPCLR) The 16-bit MPG output control register (lower) (OPCLR) controls the output of the OPT5 to OPT0 pins and the position detection interrupt. ■ Register Configuration...

  • Page 450

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit4] OPE4: OPT4 output enable bit This bit enables or disables OPT4 pin output. bit4 Details Writing "0" Disables OPT4 pin output. Writing "1" Enables OPT4 pin output. [bit3] OPE3: OPT3 output enable bit This bit enables or disables OPT3 pin output.

  • Page 451: Bit Mpg Output Data Register (upper/lower) (opdur/opdlr)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.3 16-bit MPG Output Data Register (Upper/Lower) (OPDUR/OPDLR) The 16-bit MPG output data register (upper/lower) (OPDUR/OPDLR) are two 8-bit registers storing the output data sent to the OPT5 to OPT0 pins. OPDUR is the upper byte register and OPDLR the lower byte register.

  • Page 452: Bit Mpg Output Data Register (upper) (opdur), Bit Mpg Output Data Register (upper)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.3.1 16-bit MPG Output Data Register (Upper) (OPDUR) The 16-bit MPG output data register (upper) (OPDUR) indicates data to be loaded to the OPDUR/OPDLR register from the 16-bit MPG output data buffer register (upper/lower) (OPDBRHx/OPDBRLx), and the waveform to be output to the OPT5 pin and OPT4 pin.

  • Page 453

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit1:0] OP4[1:0]: OPT4 output waveform bits These bits indicate the output waveform to the OPT4 pin. bit1:0 Details Reading "00" Indicates that "L" level is output to the OPT4 pin. Reading "01"...

  • Page 454: Bit Mpg Output Data Register (lower) (opdlr), Bit Mpg Output Data Register (lower)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.3.2 16-bit MPG Output Data Register (Lower) (OPDLR) The 16-bit MPG output data register (lower) (OPDLR) indicates the waveform to be output to the OPT3 to OPT0 pins. ■ Register Configuration Field...

  • Page 455: Bit Mpg Output Data Buffer Register (upper/lower) (opdbrhx/opdbrlx)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.4 16-bit MPG Output Data Buffer Register (Upper/ Lower) (OPDBRHx/OPDBRLx) The 16-bit MPG output data buffer register (upper/lower) consists of 12 pairs of registers (OPDBRHB to OPDBRH0 and OPDBRLB to OPDBRL0). OPDBRHx is the upper byte register and OPDBRLx the lower byte register.

  • Page 456: Bit Mpg Output Data Buffer Register (upper) (opdbrhx)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.4.1 16-bit MPG Output Data Buffer Register (Upper) (OPDBRHx) The 16-bit MPG output data buffer register (upper) (OPDBRHx) selects the pair of OPDBRHx/OPDBRLx register whose data is to be loaded to the OPDUR/ OPDLR register, and the waveform to be loaded to the OPT5 pin and OPT4 pin.

  • Page 457

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit1:0] OP4[1:0]: OPT4 output waveform select bits These bits select the output waveform to the OPT4 pin. The waveform selected is to be output to the OPT4 pin after the data in the OPDBRHx/OPDBRLx specified in the BNKF bit and RDA[2:0] bits is loaded to the OPDUR/OPDLR register.

  • Page 458: Bit Mpg Output Data Buffer Register (lower) (opdbrlx), Bit Mpg Output Data Buffer Register (lower)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.4.2 16-bit MPG Output Data Buffer Register (Lower) (OPDBRLx) The 16-bit MPG output data buffer register (lower) (OPDBRLx) selects the waveform to be output to the OPT3 to OPT0 pins. ■ Register Configuration...

  • Page 459

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit1:0] OP0[1:0]: OPT0 output waveform select bits These bits select the output waveform to the OPT0 pin. The waveform selected is to be output to the OPT0 pin after the data in the OPDBRHx/OPDBRLx specified in the BNKF bit and RDA[2:0] bits is loaded to the OPDUR/OPDLR register.

  • Page 460: Bit Mpg Input Control Register (upper/lower) (ipcur/ipclr)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.5 16-bit MPG Input Control Register (Upper/Lower) (IPCUR/IPCLR) The 16-bit MPG input control register (upper/lower) (IPCUR/IPCLR) consists of two 8-bit registers controlling position detection input. IPCUR is the upper byte register and IPCLR the lower byte register.

  • Page 461: Bit Mpg Input Control Register (upper) (ipcur), Bit Mpg Input Control Register (upper)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.5.1 16-bit MPG Input Control Register (Upper) (IPCUR) The 16-bit MPG input control register (upper) (IPCUR) controls PPG edge synchronization and the compare operation. ■ Register Configuration Field WTS1 WTS0 CPIF CPIE...

  • Page 462

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit3:1] CPD[2:0]: Compare bits These bits are used to compare with the RDA[2:0] bits in the 16-bit MPG output data register (upper) (OPCUR). When the value of the CPD[2:0] bits match the value of the RDA[2:0] bits, the compare interrupt request flag bit (CPIF) is set to "1".

  • Page 463: Bit Mpg Input Control Register (lower) (ipclr), Bit Mpg Input Control Register (lower)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.5.2 16-bit MPG Input Control Register (Lower) (IPCLR) The 16-bit MPG input control register (lower) (IPCLR) controls the input edge polarity, the noise cancellation function for the SNI2 to SNI0 pins and the edge detection on the SNI2 to SNI0 pins.

  • Page 464

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit2] SEE2: SNI2 enable bit This bit enables or disables the edge detection on the SNI2 pin. Set this bit before setting the CMPE bit in the input control register (upper) (IPCUR) to "0".

  • Page 465: Bit Mpg Compare Clear Register (upper/lower) (cpcur/cpclr)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.6 16-bit MPG Compare Clear Register (Upper/Lower) (CPCUR/CPCLR) The 16-bit MPG compare clear register (upper/lower) (CPCUR/CPCLR) consists of two 8-bit registers. CPCUR is the upper byte register and CPCLR the lower byte register. When the values of these registers match the count value of the 16-bit timer, the 16-bit timer is reset to "0x0000".

  • Page 466: Bit Mpg Timer Buffer Register (upper/lower) (tmbur/tmblr)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.7 16-bit MPG Timer Buffer Register (Upper/Lower) (TMBUR/TMBLR) The timer buffer register (upper/lower) (TMBUR/TMBLR) consists of two 8-bit registers used to read the counter value of 16-bit timer. The 16-bit MPG timer buffer register (upper) (TMBUR) and the 16-bit MPG timer buffer register (lower) (TMBLR) store the counter value of the 16-bit timer at the point at which a write timing trigger or a position detection trigger is generated.

  • Page 467: Bit Mpg Timer Control Status Register (tcsr), Bit Mpg Timer Control Status Register (tcsr)

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.8 16-bit MPG Timer Control Status Register (TCSR) The 16-bit MPG timer control status register (TCSR) controls the operation of the 16-bit timer. ■ Register Configuration Field TCLR MODE ICLR ICRE TMEN...

  • Page 468

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers [bit4] ICRE: Compare clear interrupt enable bit This bit enables or disables the compare clear interrupt. When this bit is set to "1", and the compare clear interrupt request flag bit (ICLR) is also set to "1", a compare clear interrupt is generated.

  • Page 469: Bit Mpg Noise Cancellation Control Register (nccr), Bit Mpg Noise Cancellation Control Register

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.6 Registers 21.6.9 16-bit MPG Noise Cancellation Control Register (NCCR) The 16-bit MPG noise cancellation control register (NCCR) controls the noise pulse width to be cancelled on the DTTI pin and SNIx pin. ■ Register Configuration...

  • Page 470: Notes On Using Multi-pulse Generator

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.7 Notes on Using Multi-pulse Generator 21.7 Notes on Using Multi-pulse Generator This section provides notes on using the multi-pulse generator. ■ Notes on Using Waveform Sequencer ● Notes on using a program for setting •...

  • Page 471

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.7 Notes on Using Multi-pulse Generator ● Notes on interrupts • When the DTIF bit in the 16-bit MPG output control register (upper) (OPCUR) is set to "1", control cannot be returned from interrupt processing. Always clear the DTIF bit.

  • Page 472: Sample Program For Multi-pulse Generator

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.8 Sample Program for Multi-pulse Generator 21.8 Sample Program for Multi-pulse Generator This section provides a sample program for the multi-pulse generator. ■ Sample Program for Multi-pulse Generator ● Processing • An output in the PPG is directed to OPT0 and an inverted output in the PPG is directed to OPT1 when write timing interrupt is generated.

  • Page 473

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.8 Sample Program for Multi-pulse Generator MOVW PCNT1,A ;Enables PPG output in normal polarity ;Enables 16-bit PPG timer ;Software triggers PPG ;Select PWM mod ;Clears interrupt flag, and starts counter MOVW A,#0103H MOVW OPCR,A ;Enable OPT0 and OPT1 output...

  • Page 474

    CHAPTER 21 MULTI-PULSE GENERATOR MB95630H Series 21.8 Sample Program for Multi-pulse Generator FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 475: Chapter 22 Uart/sio

    CHAPTER 22 UART/SIO This chapter describes the functions and operations of UART/SIO. 22.1 Overview 22.2 Configuration 22.3 Channel 22.4 Pins 22.5 Interrupts 22.6 Operations and Setting Procedure Example 22.7 Registers MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 476

    CHAPTER 22 UART/SIO MB95630H Series 22.1 Overview 22.1 Overview The UART/SIO is a general-purpose serial data communication interface. Serial data transfers of variable-length data can be made with a synchronous or asynchronous clock. The transfer format is NRZ. The transfer rate can be set with the dedicated baud rate generator or external clock (in clock synchronous mode).

  • Page 477

    CHAPTER 22 UART/SIO MB95630H Series 22.2 Configuration 22.2 Configuration The UART/SIO consists of the following blocks: • UART/SIO serial mode control register 1 (SMC1n) • UART/SIO serial mode control register 2 (SMC2n) • UART/SIO serial status and data register (SSRn) •...

  • Page 478

    CHAPTER 22 UART/SIO MB95630H Series 22.2 Configuration ● UART/SIO serial mode control register 1 (SMC1n) This register controls UART/SIO operation mode. It is used to set the serial data direction (endian), parity and its polarity, stop bit length, operation mode (synchronous/asynchronous), data length, and serial clock.

  • Page 479

    CHAPTER 22 UART/SIO MB95630H Series 22.3 Channel 22.3 Channel This section describes the channel of UART/SIO. ■ Channel of UART/SIO Table 22.3-1 and Table 22.3-2 show the pins and registers of UART/SIO respectively. Table 22.3-1 Pins of UART/SIO Pin name...

  • Page 480

    CHAPTER 22 UART/SIO MB95630H Series 22.4 Pins 22.4 Pins This section describes the pins of the UART/SIO. ■ Pins of UART/SIO The pins of UART/SIO are the clock input and output pin (UCKn), serial data output pin (UOn) and serial data input pin (UIn).

  • Page 481

    CHAPTER 22 UART/SIO MB95630H Series 22.5 Interrupts 22.5 Interrupts The UART/SIO has six interrupt-related bits: receive error flag bits (PER, OVE, FER), receive data register full flag bit (RDRF), transmit data register empty flag bit (TDRE), and transmission completion flag bit (TCPL).

  • Page 482

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example 22.6 Operations and Setting Procedure Example The UART/SIO has a serial communication function (operation mode 0, 1). ■ Operations of UART/SIO ● Operation mode Two operation modes are available in the UART/SIO. Clock synchronous mode (SIO) or clock asynchronous mode (UART) can be selected (See Table 22.6-1).

  • Page 483: Operations In Operation Mode 0

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example 22.6.1 Operations in Operation Mode 0 Operation mode 0 operates as clock asynchronous mode (UART). ■ Operations in UART/SIO Operation Mode 0 Clock asynchronous mode (UART) is selected when the MD bit in the UART/SIO serial mode control register 1 (SMC1n) is set to "0".

  • Page 484

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example The baud rate in clock asynchronous mode (UART) can be set in the following range. Table 22.6-3 Baud Rate Setting Range in Clock Asynchronous Mode (UART) PSS[1:0] BRS[7:0] 0b00 to 0b11 0x02 (2) to 0xFF (255) ●...

  • Page 485

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example ● Reception in asynchronous clock mode (UART) Use UART/SIO serial mode control register 1 (SMC1n) to select the serial data direction (endian), parity/non-parity, parity polarity, stop bit length, character bit length, and clock.

  • Page 486

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example ● Receive error in asynchronous clock mode (UART) If any of the following three error flags (PER, FER, OVE) has been set, receive data is not transferred to the UART/SIO serial input data register (RDRn) and the receive data register full flag bit (RDRF) is not set to "1"...

  • Page 487

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example ● Start bit detection and confirmation of receive data during reception The start bit is detected by a falling of the serial input followed by a succession of three "L"...

  • Page 488

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example ● Transmission in asynchronous clock mode Use UART/SIO serial mode control register 1 (SMC1n) to select the serial data direction (endian), parity/non-parity, parity polarity, stop bit length, character bit length, and clock.

  • Page 489

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example The TDRE bit is set at the point indicated in the following figure if the preceding piece of transmit data does not exist in the transmission shift register. Figure 22.6-7 Setting Timing 1 for Transmit Data Register Empty Flag Bit (TDRE) (When TXE is "1")

  • Page 490: Operations In Operation Mode 1

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example 22.6.2 Operations in Operation Mode 1 Operation mode 1 operates in clock synchronous mode (SIO). ■ Operations in UART/SIO Operation Mode 1 Setting the MD bit in the UART/SIO serial mode control register 1 (SMC1n) to "1" selects synchronous clock mode (SIO).

  • Page 491

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example Figure 22.6-10 Baud Rate Calculation Formula for Using Dedicated Baud Rate Generator Machine clock (MCLK) Baud rate value = [bps] × × UART prescaler select register (PSSRn) UART baud rate setting register (BRSRn)

  • Page 492

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example ● Reception in UART/SIO operation mode 1 For reception in operation mode 1, each register is used as shown below. Figure 22.6-11 Registers Used for Reception in Operation Mode 1...

  • Page 493

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example When 5-bit to 8-bit serial data is received by the reception shift register, the received data is transferred to the UART/SIO serial input data register (RDRn) and the next piece of serial data can be received.

  • Page 494

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example ● Transmission in UART/SIO operation mode 1 For transmission in operation mode 1, each register is used as shown below. Figure 22.6-14 Registers Used for Transmission in Operation Mode 1...

  • Page 495

    CHAPTER 22 UART/SIO MB95630H Series 22.6 Operations and Setting Procedure Example When the use of the external clock signal has been set, serial data transmission starts at the fall of the first serial clock signal after the transmission process is started.

  • Page 496

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers 22.7 Registers This section describes the registers of the UART/SIO. Table 22.7-1 List of UART/SIO Registers Register Register name Reference abbreviation SMC1n UART/SIO serial mode control register 1 22.7.1 SMC2n UART/SIO serial mode control register 2 22.7.2...

  • Page 497: Uart/sio Serial Mode Control Register 1 (smc1n)

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers 22.7.1 UART/SIO Serial Mode Control Register 1 (SMC1n) The UART/SIO serial mode control register 1 (SMC1n) controls the UART/SIO operation mode. The register is used to set the serial data direction (endian), parity and its polarity, stop bit length, operation mode (synchronous/ asynchronous), data length, and serial clock.

  • Page 498

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers [bit3:2] CBL[1:0]: Character bit length control bits These bits select the character bit length. The setting of these bits is valid in both clock asynchronous mode (UART) and clock synchronous mode (SIO). bit3:2 Details Writing "00"...

  • Page 499: Uart/sio Serial Mode Control Register 2 (smc2n)

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers 22.7.2 UART/SIO Serial Mode Control Register 2 (SMC2n) The UART/SIO serial mode control register 2 (SMC2n) controls the UART/SIO operation mode. The register enables or disables serial clock output, serial data output, transmission/reception, and interrupts, and clears the receive error flag.

  • Page 500

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers [bit4] RXE: Receive operation enable bit This bit enables or disables the reception of serial data. If this bit is set to "0" during a receive operation, the receive operation will be immediately disabled and initialized.

  • Page 501: Uart/sio Serial Status And Data Register (ssrn)

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers 22.7.3 UART/SIO Serial Status and Data Register (SSRn) The UART/SIO serial status and data register (SSRn) indicates the transmission/reception status and error status of the UART/SIO. ■ Register Configuration Field — — RDRF...

  • Page 502

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers [bit2] RDRF: Receive data register full flag bit This bit indicates the state of the UART/SIO serial input data register (RDRn). When receive data is loaded to the RDRn register, this bit is set to "1".

  • Page 503: Uart/sio Serial Input Data Register (rdrn), Uart/sio Serial Input Data Register (rdrn)

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers 22.7.4 UART/SIO Serial Input Data Register (RDRn) The UART/SIO serial input data register (RDRn) is used for inputting (receiving) serial data. ■ Register Configuration Field Attribute Initial value ■ Register Functions This register stores received data. The serial data signals sent to the serial data input pin (UIn) is converted by the shift register and stored in this register.

  • Page 504: Uart/sio Serial Output Data Register (tdrn), Uart/sio Serial Output Data Register (tdrn)

    CHAPTER 22 UART/SIO MB95630H Series 22.7 Registers 22.7.5 UART/SIO Serial Output Data Register (TDRn) The UART/SIO serial output data register (TDRn) used for outputting (transmitting) serial data. ■ Register Configuration Field Attribute Initial value ■ Register Functions This register holds data to be transmitted. The register accepts a write when the transmit data register empty flag bit (TDRE) is "1".

  • Page 505: Chapter 23 Uart/sio Dedicated Baud Rate Generator

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR This chapter describes the functions and operations of the dedicated baud rate generator for the UART/SIO. 23.1 Overview 23.2 Channel 23.3 Operations 23.4 Registers MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 506

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.1 Overview 23.1 Overview The UART/SIO dedicated baud rate generator generates the baud rate for the UART/SIO. The generator consists of the UART/SIO dedicated baud rate generator prescaler select register (PSSRn) and UART/SIO dedicated baud rate generator baud rate setting register (BRSRn).

  • Page 507

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.2 Channel 23.2 Channel This section describes the channel of the UART/SIO dedicated baud rate generator. ■ Channel of UART/SIO Dedicated Baud Rate Generator Table 23.2-1 shows the registers of the UART/SIO dedicated baud rate generator.

  • Page 508

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.3 Operations 23.3 Operations The UART/SIO dedicated baud rate generator serves as the baud rate generator in clock asynchronous mode (UART). ■ Baud Rate Setting The CKS bit in the SMC1n register of the UART/SIO is used to select the serial clock. This selects the UART/SIO dedicated baud rate generator.

  • Page 509

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.4 Registers 23.4 Registers This section describes the registers of the UART/SIO dedicated baud rate generator. Table 23.4-1 List of UART/SIO Baud Rate Generator Registers Register Register name Reference abbreviation PSSRn UART/SIO dedicated baud rate generator prescaler select register 23.4.1...

  • Page 510: Uart/sio Dedicated Baud Rate Generator Prescaler Select Register (pssrn)

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.4 Registers 23.4.1 UART/SIO Dedicated Baud Rate Generator Prescaler Select Register (PSSRn) The UART/SIO dedicated baud rate generator prescaler select register (PSSRn) controls the output of the baud rate clock and the prescaler.

  • Page 511: Uart/sio Dedicated Baud Rate Generator Baud Rate Setting Register (brsrn)

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.4 Registers 23.4.2 UART/SIO Dedicated Baud Rate Generator Baud Rate Setting Register (BRSRn) The UART/SIO dedicated baud rate generator baud rate setting register (BRSRn) controls the baud rate settings. ■ Register Configuration...

  • Page 512

    CHAPTER 23 UART/SIO DEDICATED BAUD RATE GENERATOR MB95630H Series 23.4 Registers FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 513

    This chapter describes functions and operations of the I C bus interface. 24.1 Overview 24.2 Configuration 24.3 Channel 24.4 Pins 24.5 Interrupts 24.6 Operations and Setting Procedure Example 24.7 Registers 24.8 Notes on Using I C Bus Interface MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 514

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.1 Overview 24.1 Overview The I C bus interface supports the I C bus specification published by Philips. The interface provides the functions of transmission and reception in master and slave modes, detection of arbitration lost, detection of slave address and general call address, generation and detection of start and stop conditions, bus error detection, and MCU standby wakeup.

  • Page 515

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.2 Configuration 24.2 Configuration The I C bus interface consists of the following blocks: • Clock selector • Clock divider • Shift clock generator • Start/stop condition generation circuit • Start/stop condition detection circuit •...

  • Page 516

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.2 Configuration ■ Block Diagram of I C Bus Interface Figure 24.2-1 Block Diagram of I C Bus Interface I C enable ICCRn Machine clock Clock divider 1 DMBP Clock selector 1...

  • Page 517: Chapter 24 I 2 C Bus Interface

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.2 Configuration ● Clock selector, clock divider, and shift clock generator This circuit uses the machine clock to generate the shift clock for the I C bus. ● Start/stop condition generation circuit When a start condition is transmitted with the bus idle (SCLn and SDAn at the "H"...

  • Page 518

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.3 Channel 24.3 Channel This section describes the channel of the I C bus interface. ■ Channel of I C Bus Interface Table 24.3-1 and Table 24.3-2 show the pins and registers on a channel of the I C bus interface respectively.

  • Page 519

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.4 Pins 24.4 Pins This section describes the pins of the I C bus interface and gives their block diagram. ■ Pins of I C Bus Interface The pins of the I C bus interface are SDAn and SCLn.

  • Page 520

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.5 Interrupts 24.5 Interrupts The I C bus interface has a transfer interrupt and a stop interrupt which are triggered by the following events. • Transfer interrupt A transfer interrupt occurs either upon completion of data transfer or when a bus error occurs.

  • Page 521

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.5 Interrupts ■ Stop Interrupt Table 24.5-2 shows the stop interrupt control bits and I C interrupt sources (trigger events). Table 24.5-2 Stop Interrupt Control Bits and I C Interrupt Sources MCU wakeup from...

  • Page 522

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example 24.6 Operations and Setting Procedure Example This section describes the operations of the I C bus interface. ■ Operations of I C Bus Interface ● I...

  • Page 523

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example 24.6.1 C Bus Interface The I C bus interface is an eight-bit serial interface synchronized with the shift clock. It conforms to the I C bus specification defined by Philips.

  • Page 524

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example ■ Start Conditions While the bus is idle (SCLn and SDAn are both at the logical "H" level), the master generates a start condition to start transmission. As shown in Figure 24.6-1, a start condition is triggered when the SDAn line is changed from "H"...

  • Page 525

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example ■ Acknowledgment An acknowledgment is sent by the receiver in the ninth clock cycle for data byte transfer by the sender based on the following conditions.

  • Page 526

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example ■ General Call Address A general call address consists of the start address byte (0x00) and the second address byte that follows. To use a general call address, you must set IBCR1n:GACKE=1 before the acknowledge of the first byte general call address.

  • Page 527

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example ■ Stop Condition The master can release the bus and end communications by generating a stop condition. Changing the SDAn line from "L" to "H" while SCLn is "H" generates a stop condition. This signals to the other devices on the bus that the master has finished communications (referred to below as "bus free").

  • Page 528

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example Figure 24.6-3 Timing Diagram with No Interrupt Generated with IBCR0n:ALF = 1 SCLn pin or SDAn pin at "L" level "L" SCLn pin "L" SDAn pin...

  • Page 529

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example • Conditions (2) in which no interrupt is generated due to arbitration lost If the program enables I C bus interface operation (by setting the ICCRn:EN bit to "1") and triggers a start condition (by setting the IBCR1n:MSS bit to "1") when the I...

  • Page 530

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example The following sample flow chart illustrates the procedure: Figure 24.6-5 Sample Flow Chart 1 Enable AL interrupts (IBCR0n:ALE =1). Set master mode. Set the MSS bit in I C bus control register 1 (IBCR1n) to "1".

  • Page 531: Function To Wake Up The Mcu From Standby Mode

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example 24.6.2 Function to Wake up the MCU from Standby Mode The wakeup function enables the I C macro to be accessed while the MCU is in stop or watch mode.

  • Page 532

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.6 Operations and Setting Procedure Example The following sample flow chart illustrates the wakeup function. Figure 24.6-8 Sample Flow Chart 2 Procedure for transition to stop/watch mode IBSRn:BB = 0 Enable wakeup function by setting IBCR0n:WUE =1.

  • Page 533

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7 Registers This section describes the registers of the I C bus interface. Table 24.7-1 List of I C Bus Interface Registers Register Register name Reference abbreviation IBCR0n 24.7.1 C bus control register 0 IBCR1n 24.7.2...

  • Page 534

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7.1 C Bus Control Register 0 (IBCR0n) The I C bus control register 0 (IBCR0n) controls the address acknowledge in the transmission of the first byte, selects the timing of the transfer completion interrupt, and enables or disables the arbitration lost interrupt, the STOP condition detection interrupt and MCU standby wakeup function.

  • Page 535

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers • The latest data acknowledge (IBSRn:LRB) can be read after the acknowledge has been received (IBSRn:LRB must be read during the transfer completion interrupt in the ninth SCLn cycle.) If acknowledge is read when this bit is "1", therefore, you must write "0"...

  • Page 536

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers [bit2] SPE: STOP detection interrupt enable bit This bit enables or disables the STOP detection interrupt. When this bit and the SPF bit are both set to "1", a STOP detection interrupt request is generated.

  • Page 537

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7.2 C Bus Control Register 1 (IBCR1n) The I C bus control register 1 (IBCR1n) controls the following functions: bus error interrupt, START condition generation, master/slave mode selection, data acknowledge, general call acknowledge and transfer completion interrupt.

  • Page 538

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers [bit5] SCC: START condition generation bit This bit generates a repeated START condition to restart communications in master mode. In master mode, writing "1" to this bit generates a repeated START condition.

  • Page 539

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers [bit2] GACKE: General call address acknowledge enable bit This bit controls the general call address acknowledge. Writing "0" to this bit disables general call address acknowledge output. With this bit set to "1", in master mode or slave mode, when a general call address acknowledge (0x00) is received, a general call address acknowledge is output.

  • Page 540

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers Notes: • When clearing the interrupt request flag bit (IBCR1n:BER) by writing "0" to it, do not update the interrupt request enable bit (IBCR1n:BEIE) at the same time. • All bits in the IBCR1n register except the BER and BEIE bits are cleared to "0" either...

  • Page 541

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7.3 C Bus Status Register (IBSRn) The I C bus status register (IBSRn) indicates the status of the I C bus interface. ■ Register Configuration Field — Attribute — Initial value ■...

  • Page 542

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers [bit4] LRB: Acknowledge storage bit This bit captures the value of the SDAn line in the ninth shift clock cycle during data byte transfer. This bit is set to "1" when no acknowledge has been detected (SDAn = "H").

  • Page 543

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers [bit1] GCA: General call address detection bit This bit detects a general call address. If one of the following conditions is satisfied, this bit is set to "1". • The device receives a general call address (0x00) in slave mode.

  • Page 544

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7.4 C Data Register (IDDRn) The I C data register (IDDRn) sets the data or address to be transmitted, and holds the data or address received. ■ Register Configuration Field...

  • Page 545

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7.5 C Address Register (IAARn) The I C address register (IAARn) register sets the slave address. In slave mode, the I C bus interface receives address data from the master and compares it with the value of this register.

  • Page 546

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers 24.7.6 C Clock Control Register (ICCRn) The I C clock control register (ICCRn) register enables the I C operation and selects the shift clock frequency. ■ Register Configuration Field DMBP —...

  • Page 547

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.7 Registers [bit4:3] CS[4:3]: Clock-1 select bits (Divider m) [bit2:0] CS[2:0]: Clock-2 select bits (Divider n) These bits set the shift clock frequency. The shift clock frequency (Fsck) is set by the following equation: φ...

  • Page 548

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.8 Notes on Using I C Bus Interface 24.8 Notes on Using I C Bus Interface This section provides notes on using the I C bus interface. ■ Notes on Using I C Bus Interface ●...

  • Page 549

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.8 Notes on Using I C Bus Interface ● Notes on selecting the transfer complete timing • The transfer complete timing select bit (IBCR0n:INTS) is valid only during data reception (IBSRn:TRX = 0 and IBSRn:FBT = 0).

  • Page 550

    CHAPTER 24 I C BUS INTERFACE MB95630H Series 24.8 Notes on Using I C Bus Interface FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 551

    25.1 Overview 25.2 Sector/Bank Configuration 25.3 Invoking Flash Memory Automatic Algorithm 25.4 Checking Automatic Algorithm Execution Status 25.5 Programming/Erasing Flash Memory 25.6 Operations 25.7 Flash Security 25.8 Registers 25.9 Notes on Using Dual Operation Flash Memory MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 552

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.1 Overview 25.1 Overview The dual operation Flash memory is located at 0x1000 to 0x1FFF and at 0xF000 to 0xFFFF for 64 Kbit Flash memory, at 0x1000 to 0x1FFF and at 0xE000 to...

  • Page 553

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.1 Overview ■ Features of Dual Operation Flash Memory • Sector configuration - 8 Kbyte × 8 bits (4 Kbyte + 2 Kbyte × 2) - 12 Kbyte × 8 bits (8 Kbyte + 2 Kbyte × 2) - 20 Kbyte ×...

  • Page 554: Sector/bank Configuration

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.2 Sector/Bank Configuration 25.2 Sector/Bank Configuration This section shows the sector/bank configuration of the Flash memory. ■ Sector/Bank Configuration of Dual Operation Flash Memory Figure 25.2-1 shows the sector configuration of the Dual operation Flash memory. The upper and lower addresses of each sector are shown in the figure.

  • Page 555: Invoking Flash Memory Automatic Algorithm

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.3 Invoking Flash Memory Automatic Algorithm 25.3 Invoking Flash Memory Automatic Algorithm There are four commands that invoke the Flash memory automatic algorithm: read/reset, program, chip erase, and sector erase. The sector erase command is capable of suspending and resuming sector erase.

  • Page 556

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.3 Invoking Flash Memory Automatic Algorithm Notes: • Addresses in Table 25.3-1 are values on the CPU memory map. All addresses and data are in hexadecimal notation. However, "X" is an arbitrary value.

  • Page 557: Checking Automatic Algorithm Execution Status

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status 25.4 Checking Automatic Algorithm Execution Status Since the Flash memory uses the automatic algorithm to execute the program/ erase flow, its internal operating status can be checked through the hardware sequence flags.

  • Page 558

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status ● Description of hardware sequence flags Table 25.4-2 lists the functions of the hardware sequence flags. Table 25.4-2 List of Hardware Sequence Flag Functions State Programming → Programming completed DQ7 →...

  • Page 559: Data Polling Flag (dq7), Data Polling Flag (dq)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status 25.4.1 Data Polling Flag (DQ7) The data polling flag (DQ7) is a hardware sequence flag indicating that the automatic algorithm is being executing or has been completed using the data polling function.

  • Page 560

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status Note: Once the automatic algorithm has been started, read access to the specified address is ignored. Data reading is allowed after the data polling flag (DQ7) is set to "1". Data reading after the end of the automatic algorithm should be performed following read access made to confirm the completion of data polling.

  • Page 561: Toggle Bit Flag (dq6), Toggle Bit Flag (dq)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status 25.4.2 Toggle Bit Flag (DQ6) The toggle bit flag (DQ6) is a hardware sequence flag using the toggle bit function to indicate whether the automatic algorithm is being executed or has terminated.

  • Page 562: Execution Timeout Flag (dq5), Execution Timeout Flag (dq)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status 25.4.3 Execution Timeout Flag (DQ5) The execution timeout flag (DQ5) is a hardware sequence flag indicating that the execution time of the automatic algorithm exceeds a specified time (required for programming/erasing) in the Flash memory.

  • Page 563: Sector Erase Timer Flag (dq3), Sector Erase Timer Flag (dq)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status 25.4.4 Sector Erase Timer Flag (DQ3) The sector erase timer flag (DQ3) is a hardware sequence flag indicating whether the Flash memory is waiting for sector erase after the sector erase command has started.

  • Page 564: Toggle Bit2 Flag (dq2), Toggle Bit2 Flag (dq)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.4 Checking Automatic Algorithm Execution Status 25.4.5 Toggle Bit2 Flag (DQ2) The toggle bit2 flag (DQ2) is a hardware sequence flag using the toggle bit function to indicate whether a read address is an erase target sector in the sector erase suspend state and whether output data is toggled.

  • Page 565: Programming/erasing Flash Memory

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5 Programming/Erasing Flash Memory This section describes the respective procedures for reading/resetting the Flash memory, programming, chip-erasing, sector-erasing, sector erase suspending and sector erase resuming by entering respective commands to invoke the automatic algorithm.

  • Page 566: Placing Flash Memory In Read/reset State

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.1 Placing Flash Memory in Read/Reset State This section explains the procedure for entering the read/reset command to place the Flash memory in read/reset state. ■ Placing Flash Memory in Read/Reset State •...

  • Page 567: Programming Data To Flash Memory

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.2 Programming Data to Flash Memory This section explains the procedure for entering the program command to program data to the Flash memory. ■ Programming Data to Flash Memory •...

  • Page 568

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory Figure 25.5-1 Sample Procedure for Programming to Flash Memory Start of programming FSR:WRE Enable Flash memory programming. SWRE0 Enable/disable programming data to a sector. (Write "0" to disable programming data or “1” to enable programming data to a sector.)

  • Page 569: Erasing All Data From Flash Memory (chip Erase)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.3 Erasing All Data from Flash Memory (Chip Erase) This section explains the procedure for issuing the chip erase command to erase all data in the Flash memory.

  • Page 570: Erasing Specific Data From Flash Memory (sector Erase)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.4 Erasing Specific Data from Flash Memory (Sector Erase) This section explains the procedure for entering the sector erase command to erase a specific sector in the Flash memory. Sector-by-sector erase is enabled and multiple sectors can also be specified at a time.

  • Page 571

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory Figure 25.5-2 Sample Procedure for Erasing Data from Sectors in Flash Memory Start of erasing FSR:WRE Enable Flash memory erasing. SWRE0 Enable/disable programming data to a sector. (Write "0" to disable programming data or “1” to enable programming data to a sector.)

  • Page 572: Suspending Sector Erase From Flash Memory

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.5 Suspending Sector Erase from Flash Memory This section explains the procedure for entering the sector erase suspend command to suspend sector erase from the Flash memory. Data can be read from sectors not being erased.

  • Page 573: Resuming Sector Erase Of Flash Memory

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.6 Resuming Sector Erase of Flash Memory This section explains the procedure for entering the sector erase resume command to resume suspended erasing of a sector in the Flash memory.

  • Page 574: Unlock Bypass Program

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.5 Programming/Erasing Flash Memory 25.5.7 Unlock Bypass Program This sections explains details of the unlock bypass state. ■ Transiting from Normal Command State to Unlock Bypass State If an unlock bypass program command is input in the normal command state, the Flash memory will transit to the unlock bypass state.

  • Page 575

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.6 Operations 25.6 Operations Pay attention in particular to the following points when using dual operation Flash memory: • Interrupt generated when upper banks are updated • Procedure of setting the sector swap enable bit in the flash memory status register (FSR:SSEN) ■...

  • Page 576

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.6 Operations ■ Operation during Programming/Erasing It is prohibited to program data to the Flash memory within an interrupt routine when an interrupt occurs during Flash memory programming/erasing. When two or more program/erase routines exist, wait for one program/erase routine to finish before executing another program/erase routine.

  • Page 577: Flash Security

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.7 Flash Security 25.7 Flash Security The Flash security controller function prevents contents of the Flash memory from being read by external pins. ■ Flash Security Writing protection code "0x01" to the Flash memory address (0xFFFC) restricts access to the Flash memory, disabling any read/write access to the Flash memory from any external pin.

  • Page 578

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers 25.8 Registers This section describes the registers for the Flash memory. Table 25.8-1 List of Flash Memory Registers Register Register name Reference abbreviation FSR2 Flash memory status register 2 25.8.1 Flash memory status register 25.8.2...

  • Page 579: Flash Memory Status Register 2 (fsr2), Flash Memory Status Register 2 (fsr)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers 25.8.1 Flash Memory Status Register 2 (FSR2) This section describes the Flash memory status register 2 (FSR2). ■ Register Configuration Field PEIEN PGMEND PTIEN PGMTO EEIEN ERSEND ETIEN ERSTO Attribute Initial value ■...

  • Page 580

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers [bit5] PTIEN: PGMTO interrupt enable bit This bit enables or disables the generation of interrupt requests triggered by the failure of Flash memory programming. bit5 Details Writing "0" Disables the interrupt request upon failure of Flash memory programming (FSR2:PGMTO = 1).

  • Page 581

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers [bit1] ETIEN: ERSTO interrupt enable bit This bit enables or disables the generation of interrupt requests triggered by the failure of Flash memory sector erase. bit1 Details Writing "0" Disables the interrupt request upon failure of Flash memory sector erase (FSR2:ERSTO = 1).

  • Page 582: Flash Memory Status Register (fsr), Flash Memory Status Register (fsr)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers 25.8.2 Flash Memory Status Register (FSR) This section describes the Flash memory status register (FSR). ■ Register Configuration Field — — RDYIRQ Reserved IRQEN SSEN Attribute — — Initial value ■...

  • Page 583

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers [bit2] IRQEN: Flash memory program/erase interrupt enable bit This bit enables or disables the generation of interrupt requests triggered by the completion of Flash memory programming/erasing. bit2 Details Writing "0"...

  • Page 584

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers Figure 25.8-1 Access Sector Map by FSR:SSEN Value MB95F632H/F632K MB95F633H/F633K CPU address CPU address 0x1000 0x1000 SA0: 2 Kbyte SA0: 2 Kbyte SA0: 2 Kbyte SA0: 2 Kbyte 0x17FF 0x17FF...

  • Page 585: Flash Memory Sector Write Control Register 0 (swre0)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers 25.8.3 Flash Memory Sector Write Control Register 0 (SWRE0) The flash memory sector write control register 0 (SWRE0) is installed in the Flash memory interface and used to set the function of protecting the Flash memory against spurious writes.

  • Page 586

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers Settings of SAxE (x = 0, 1 or 2) and their respective programming functions: • Program-disabled (SAxE = 0): With "0" not written to the SAxE bit in the flash memory sector write control register 0 (SWRE0), programming data to a sector can be enabled by setting the SAxE bit corresponding to that sector to "1".

  • Page 587: Flash Memory Status Register 3 (fsr3), Flash Memory Status Register 3 (fsr)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers 25.8.4 Flash Memory Status Register 3 (FSR3) This section describes the flash memory status register 3 (FSR3). ■ Register Configuration Field — — — CERS ESPS SERS PGMS HANG Attribute —...

  • Page 588: Flash Memory Status Register 4 (fsr4), Flash Memory Status Register 4 (fsr)

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers 25.8.5 Flash Memory Status Register 4 (FSR4) This section describes of the flash memory status register 4 (FSR4). ■ Register Configuration Field — CEREND CTIEN CERTO — — — —...

  • Page 589

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers [bit4] CERTO: CERTO interrupt request flag bit This bit indicates that Flash memory chip erase has failed. When Flash memory chip erase fails, the CERTO bit is set to "1" upon completion of the Flash memory automatic algorithm.

  • Page 590

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers ■ Examples of Status of Flash Memory Status Register 2, Flash Memory Status Register 3, Flash Memory Status Register 4 and RDY Bit (FSR:RDY) Figure 25.8-3 FSR2:PGMEND during Flash Memory Programming...

  • Page 591

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers Figure 25.8-6 FSR2:ERSTO when Flash Memory Sector Erase Failed Sector erase command Sector erase timeout Reset command FSR:RDY FSR3:PGMS FSR3:SERS FSR3:ESPS FSR3:HANG FSR2:ERSTO Figure 25.8-7 FSR2:PGMEND and FSR2:ERSEND when Flash Memory Programming Is in...

  • Page 592

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers Figure 25.8-9 FSR2:ERSEND when Flash Memory Read Is in Progress with Flash Memory Sector Erase Suspended Sector erase Sector erase Sector erase suspend Reset command suspend command command (read) resume command...

  • Page 593

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers Figure 25.8-12 FSR4:CEREND during Chip Erase Chip erase Chip erase command FSR:RDY FSR3:CERS FSR3:SERS FSR4:CEREND MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 594

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers ■ Flash Memory Sector Write Control Register 0 (SWRE0) Setup Flow Chart Set the FSR:WRE bit to "1" to enable Flash memory programming, then enable or disable programming data into a sector by setting the corresponding bit in the SWRE0 register to "1"...

  • Page 595

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.8 Registers ■ Note on Setting (FSR:WRE) To program data to the Flash memory, set the WRE bit to "1" to enable Flash memory programming and then set the bit in the SWRE0 register corresponding to a sector to which data is to be written.

  • Page 596: Notes On Using Dual Operation Flash Memory

    CHAPTER 25 DUAL OPERATION FLASH MEMORY MB95630H Series 25.9 Notes on Using Dual Operation Flash Memory 25.9 Notes on Using Dual Operation Flash Memory This section provides notes on using the dual operation Flash memory. ■ Restriction on Using Toggle Bit Flag (DQ6)

  • Page 597: Chapter 26 Non-volatile Register (nvr) Interface

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE This chapter describes the functions and operations of the NVR interface. 26.1 Overview 26.2 Configuration 26.3 Registers 26.4 Notes on Main CR Clock Trimming 26.5 Notes on Using NVR Interface MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 598

    After a reset, data in the NVR Flash area will be fetched and stored in registers in the NVR I/O area. In the MB95630H Series, the NVR interface is used to store the following data: • Coarse trimming value for main CR Clock (5 bits) •...

  • Page 599

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.2 Configuration 26.2 Configuration The NVR interface consists of the following blocks: • Trimming of Main CR Clock (CRTH and CRTL) • Watchdog Timer Selection ID (WDTH and WDTL) • Main CR Temperature Dependent Adjustment (CRTDA) ■...

  • Page 600

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.3 Registers 26.3 Registers This section lists the registers of the NVR interface. Table 26.3-1 List of NVR Interface Registers Register Register name Reference abbreviation CRTH Main CR clock trimming register (upper) 26.3.1...

  • Page 601: Main Cr Clock Trimming Register (upper) (crth), Main Cr Clock Trimming Register (upper) (crth)

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.3 Registers 26.3.1 Main CR Clock Trimming Register (Upper) (CRTH) This section describes the main CR clock trimming register (upper) (CRTH). ■ Register Configuration Field — — — CRTH4 CRTH3 CRTH2 CRTH1...

  • Page 602: Main Cr Clock Trimming Register (lower) (crtl), Main Cr Clock Trimming Register (lower) (crtl)

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.3 Registers 26.3.2 Main CR Clock Trimming Register (Lower) (CRTL) This section describes the main CR clock trimming register (lower) (CRTL). ■ Register Configuration Field — — — CRTL4 CRTL3 CRTL2 CRTL1...

  • Page 603: Main Cr Clock Temperature Dependent Adjustment Register (crtda)

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.3 Registers 26.3.3 Main CR Clock Temperature Dependent Adjustment Register (CRTDA) This section describes the main CR clock temperature dependent adjustment register (CRTDA). ■ Register Configuration Field — — — CRTDA4 CRTDA3...

  • Page 604: Watchdog Timer Selection Id Register (upper/lower) (wdth/wdtl)

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.3 Registers 26.3.4 Watchdog Timer Selection ID Register (Upper/Lower) (WDTH/WDTL) This section describes the watchdog timer selection ID register (upper/lower) (WDTH/WDTL). ■ Register Configuration WDTH Field WDTH7 WDTH6 WDTH5 WDTH4 WDTH3 WDTH2...

  • Page 605: Notes On Main Cr Clock Trimming

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.4 Notes on Main CR Clock Trimming 26.4 Notes on Main CR Clock Trimming This section provides notes on main CR clock trimming. After a hardware reset, the 10-bit main CR clock trimming value and the 5-bit temperature dependent adjustment value will be loaded from the NVR Flash area to registers in the NVR I/O area.

  • Page 606

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.4 Notes on Main CR Clock Trimming The relationship between main CR clock frequency and trimming step size is shown in the diagram below. Figure 26.4-1 Relationship between Main CR Clock Frequency and Trimming Step Size...

  • Page 607: Notes On Using Nvr Interface

    2. The trimming value has been preset before this device is shipped. If the preset trimming value is modified after the device has been shipped, Fujitsu Semiconductor does not warrant proper operation of the device with respect to use based on the modified trimming value.

  • Page 608

    CHAPTER 26 NON-VOLATILE REGISTER (NVR) INTERFACE MB95630H Series 26.5 Notes on Using NVR Interface FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 609: Chapter 27 Comparator

    CHAPTER 27 COMPARATOR This chapter describes the functions and operations of the comparator. 27.1 Overview 27.2 Configuration 27.3 Pins 27.4 Interrupt 27.5 Operations and Setting Procedure Example 27.6 Register MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 610

    CHAPTER 27 COMPARATOR MB95630H Series 27.1 Overview 27.1 Overview The comparator monitors the two analog input voltages, and automatically generates an interrupt upon detection of a change in the edge of comparator output. ■ Function of Comparator The function of the comparator is to monitor the two analog input voltages and compare them.

  • Page 611

    CHAPTER 27 COMPARATOR MB95630H Series 27.2 Configuration 27.2 Configuration The comparator module consists of the following blocks: • Comparator • Edge detection circuit • Comparator control register ■ Block Diagram of Comparator Figure 27.2-1 Block Diagram of Comparator Comparator control register (CMR0C)

  • Page 612

    CHAPTER 27 COMPARATOR MB95630H Series 27.2 Configuration ● Comparator The comparator monitors the voltages of two external analog inputs and compares them. Using the voltage of the non-inverting analog input (positive input) as a reference voltage, the comparator outputs "H" if the voltage of the inverting analog input (negative input) is lower than the reference voltage;...

  • Page 613

    CHAPTER 27 COMPARATOR MB95630H Series 27.3 Pins 27.3 Pins This section describes the pins of the comparator. ■ Pins of Comparator Table 27.3-1shows details of the pins of the comparator. Table 27.3-1 Pins of Comparator Pin name Pin function CMPn_P...

  • Page 614

    CHAPTER 27 COMPARATOR MB95630H Series 27.4 Interrupt 27.4 Interrupt The voltage generator generates an interrupt called output edge detection interrupt. An interrupt request number and an interrupt vector are assigned to the interrupt. ■ Output Edge Detection Interrupt Table 27.4-1 shows details of the output edge detection interrupt.

  • Page 615

    CHAPTER 27 COMPARATOR MB95630H Series 27.5 Operations and Setting Procedure Example 27.5 Operations and Setting Procedure Example The comparator can be activated by the software according to the setting of the PD bit in the CMR0C register. ■ Software Activation of Comparator The settings shown in Figure 27.5-1 are required for activating the comparator using the...

  • Page 616

    CHAPTER 27 COMPARATOR MB95630H Series 27.6 Register 27.6 Register This section describes the register of the comparator. Table 27.6-1 List of Comparator Register Register Register name Reference abbreviation CMR0C Comparator control register 27.6.1 FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 617: Comparator Control Register (cmr0c), Comparator Control Register (cmr0c)

    CHAPTER 27 COMPARATOR MB95630H Series 27.6 Register 27.6.1 Comparator Control Register (CMR0C) The comparator control register has the following functions: • To power up or power down the comparator (CMR0C:PD) • To enable or disable comparator output (CMR0C:VCOE) • To enable and disable comparator analog input (CMR0C:VCID) Except in stop mode, watch mode or time-base timer mode, if CMR0C:IE has been set to "1", upon detection of a rising edge or falling edge of comparator...

  • Page 618

    CHAPTER 27 COMPARATOR MB95630H Series 27.6 Register [bit3] IE: Interrupt request enable bit This bit enables or disables the interrupt request of the comparator. Writing "0" to this bit disables the interrupt request of the comparator. Writing "1" to this bit enables the interrupt request of the comparator. With the interrupt request enabled, the comparator generates an interrupt request when detecting an output rising edge or an output falling edge.

  • Page 619: Chapter 28 System Configuration Controller

    CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER This chapter describes the functions and operations of the system configuration controller (called the "controller" in this chapter). 28.1 Overview 28.2 Register 28.3 Notes on Using Controller MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 620

    CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER MB95630H Series 28.1 Overview 28.1 Overview The controller consists of the system configuration register (SYSC), which is an 8-bit register used to configure the clock and reset system, and to select 8/16-bit PPG ports. ■ Functions of SYSC •...

  • Page 621

    CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER MB95630H Series 28.2 Register 28.2 Register This section describes the register of the controller. Table 28.2-1 List of Voltage Comparator Register Register Register name Reference abbreviation SYSC System configuration register 28.2.1 MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 622: System Configuration Register (sysc), System Configuration Register (sysc)

    CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER MB95630H Series 28.2 Register 28.2.1 System Configuration Register (SYSC) This section describes the system configuration register. ■ Register Configuration Field PGSEL PFSEL Reserved Reserved EC0SL PPGSEL RSTOE RSTEN Attribute Initial value ■ Register Functions [bit7] PGSEL: PG1 and PG2 function select bit This bit selects the function of the PG1 and PG2 pins.

  • Page 623

    CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER MB95630H Series 28.2 Register [bit2] PPGSEL: 8/16-bit PPG output pins select bit This bit selects the 8/16-bit PPG output pins. bit2 Details Writing "0" Selects P10, P11, and P13 to P16 as 8/16-bit PPG output pins.

  • Page 624: Notes On Using Controller

    CHAPTER 28 SYSTEM CONFIGURATION CONTROLLER MB95630H Series 28.3 Notes on Using Controller 28.3 Notes on Using Controller This section provides notes on using the controller. ■ Notes on Using Controller ● Setting PPGSEL to "0" when using the multi-pulse generator (MPG) While the MPG is in use, P62 to P67 are being used as MPG output ports.

  • Page 625: Appendix

    APPENDIX This section provides an overview of instructions. Addressing Special Instruction Bit Manipulation Instructions (SETB, CLRB) MC-8FX Instructions Instruction Map MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 626: Appendix A Instruction Overview

    APPENDIX A Instruction Overview MB95630H Series APPENDIX A Instruction Overview This section explains the instructions used in F MC-8FX. ■ Instruction Overview of F MC-8FX In the F MC-8FX, there are 140 kinds of one byte instructions (256 bytes on the map), and the instruction code is composed of the instruction and the operand following it.

  • Page 627

    APPENDIX A Instruction Overview MB95630H Series ■ Meanings of Signs in Instruction Codes Table A-1 shows the meanings of signs used in explaining instruction codes in APPENDIX A. Table A-1 Meanings of Signs in Instruction Codes Sign Meanings Direct address (8-bit length)

  • Page 628

    APPENDIX A Instruction Overview MB95630H Series ■ Meanings of Items in Instruction Table Table A-2 Meanings of Items in Instruction Table Item Meaning MNEMONIC It shows the assembly description of the instruction. It shows the number of cycles of the instruction. One instruction cycle is a machine cycle.

  • Page 629: A.1 Addressing

    APPENDIX A Instruction Overview MB95630H Series A.1 Addressing Addressing MC-8FX has the following ten types of addressing: • Direct addressing • Extended addressing • Bit direct addressing • Index addressing • Pointer addressing • General-purpose register addressing • Immediate addressing •...

  • Page 630

    APPENDIX A Instruction Overview MB95630H Series A.1 Addressing ● Bit direct addressing This is used when accessing the direct area of "0x0000" to "0x047F" in bit unit with addressing indicated "dir:b" in instruction table. In this addressing, when the operand address is "0x00" to "0x7F", it is accessed into "0x0000"...

  • Page 631

    APPENDIX A Instruction Overview MB95630H Series A.1 Addressing Figure A.1-6 Example of General-purpose Register Addressing MOV A, R 6 0b01010 0xAB 0xAB 0x0156 ● Immediate addressing This is used when immediate data is needed in addressing shown "#d8" in the instruction table.

  • Page 632

    APPENDIX A Instruction Overview MB95630H Series A.1 Addressing ● Relative addressing This is used when branching to the area in 128 bytes before and behind PC (program counter) with the addressing shown "rel" in the instruction table. In this addressing, add the content of the operand to PC with the sign and store the result in PC.

  • Page 633: A.2 Special Instruction, Special Instruction

    APPENDIX A Instruction Overview MB95630H Series A.2 Special Instruction Special Instruction This section explains special instructions other than the addressings. ■ Special Instruction ● JMP @A This instruction is to branch the content of A (accumulator) to PC (program counter) as an address.

  • Page 634

    APPENDIX A Instruction Overview MB95630H Series A.2 Special Instruction Figure A.2-3 shows a summary of the instruction. Figure A.2-3 MULU A (Before executing) (After executing) 0x5678 0x1860 0x1234 0x1234 ● DIVU A This instruction divides the 16-bit value in T by the unsigned 16-bit value in A, and stores the 16-bit result and the 16-bit remainder in A and T, respectively.

  • Page 635

    APPENDIX A Instruction Overview MB95630H Series A.2 Special Instruction Figure A.2-6 shows an assembler language example. Figure A.2-6 Example of Using "XCHW A, PC" (Main routine) (Subroutine) MOVW A, #PUTSUB PUTSUB XCHW A, PC PUSHW A PTS1 MOV A, @EP...

  • Page 636

    APPENDIX A Instruction Overview MB95630H Series A.2 Special Instruction Table A.2-1 Vector Table Vector table address Vector use (call instruction) Upper Lower CALLV #7 0xFFCE 0xFFCF CALLV #6 0xFFCC 0xFFCD CALLV #5 0xFFCA 0xFFCB CALLV #4 0xFFC8 0xFFC9 CALLV #3...

  • Page 637: A.3 Bit Manipulation Instructions (setb, Clrb)

    APPENDIX A Instruction Overview MB95630H Series A.3 Bit Manipulation Instructions (SETB, CLRB) Bit Manipulation Instructions (SETB, CLRB) Some peripheral function registers include bits that are read differently than usual by a bit manipulation instruction. ■ Read-modify-write Operation By using these bit manipulation instructions, you can set only the specified bit in a register or RAM location to "1"...

  • Page 638

    APPENDIX A Instruction Overview MB95630H Series A.4 F MC-8FX Instructions MC-8FX Instructions Table A.4-1 to Table A.4-4 show the instructions used by F MC-8FX. ■ Transfer Instructions Table A.4-1 Transfer Instructions MNEMONIC Operation TL TH AH N OPCODE 2 (dir) ← (A)

  • Page 639

    APPENDIX A Instruction Overview MB95630H Series A.4 F MC-8FX Instructions Note: In automatic transfer to T during byte transfer to A, AL is transferred to TL. If an instruction has plural operands, they are saved in the order indicated by MNEMONIC.

  • Page 640

    APPENDIX A Instruction Overview MB95630H Series A.4 F MC-8FX Instructions Table A.4-2 Arithmetic Operation Instruction (1/2) MNEMONIC Operation TL TH AH N OPCODE 1 (A) ← (AL) 50 AND A, Ri (Ri) 68 to 6F 1 (A) ← (AL) 51 OR (TL) 2 (A) ←...

  • Page 641: Appendix A Instruction Overview, Instruction Map

    APPENDIX A Instruction Overview MB95630H Series A.5 Instruction Map Instruction Map Table A.5-1 shows the instruction map of F MC-8FX. ■ Instruction Map Table A.5-1 Instruction Map of F MC-8FX MN702-00009-1v0-E FUJITSU SEMICONDUCTOR LIMITED...

  • Page 642

    APPENDIX A Instruction Overview MB95630H Series A.5 Instruction Map FUJITSU SEMICONDUCTOR LIMITED MN702-00009-1v0-E...

  • Page 643

    MN702-00009-1v0-E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL 8-BIT MICROCONTROLLER New 8FX MB95630H Series HARDWARE MANUAL February 2012 the first edition FUJITSU SEMICONDUCTOR LIMITED Published Sales Promotion Department Edited...

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