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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
❍ Return by a reset request
The system status changes from sleep status to ordinary operation status in the following order:
1. Internal reset generation
2. restart of supplying the internal bus clock signal
3. restart of supplying the internal CPU clock signal
4. fetching the reset vector
5. restart of instruction execution from the reset entry address
Notes:
•
An instruction following the instruction for writing to STCR may be able to complete its
operation. So, if an interrupt request cancellation instruction or branch instruction is issued
immediately after that instruction, the operation results appear to be other than expected.
•
If an interrupt request was already generated from a peripheral, sleep status is not entered.
•
To use DMA in sleep status, enter the single chip mode in advance. This setting cannot be
used when an external bus is used.
•
Set the clock doubler to OFF before the sleep status is entered.
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