Fujitsu MB91150 Series Hardware Manual page 289

Sample interrupt routine
(1) PDRR incremented
(2) Interrupt source cleared
(3) PDRR decremented
(4) RETI
When an interrupt request is issued, the interrupt level is changed. If this level is higher than the
level specified in the HRCL register, the HRCR is activated for the DMA. This causes the DMA
to cancel the hold request. The CPU returns from the hold state and performs interrupt handling.
The interrupt routine increments PDRR and clears the interrupt source. This causes the
interrupt level to vary, inactivates the HRCR, and allows the DMA to issue a hold request again.
However, because the PDRR is not 0, this hold request is blocked. To enable DMA transfer
again, decrement the PDRR to pass the hold request to the CPU.
❍ Example for multiple interrupt routine
Figure 12.7-3 "Sample timing of the hold-request cancellation-request sequence
(HRCL > a > b)" is a sample timing chart for multiple interrupts.
Figure 12.7-3 Sample timing of the hold-request cancellation-request sequence (HRCL > a > b)
RUN Bus hold
CPU
DHRQ
HRQ
HACK
IRQ1
IRQ2
LEVEL
HRCR
PDRR 0000
Interrupt I Interrupt handling II
(1) (5) (6)
a b
0001 0002
CHAPTER 12 INTERRUPT CONTROLLER
Interrupt handling I
(7)(8) (2) (3) (4)
a
0001
Bus hold
0000
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