Fujitsu MB91150 Series Hardware Manual page 385

[Bits 19, 11, and 3] AKSEn
[Bits 18, 10, and 2] AKDEn
Specify the time at which to generate a transfer-request-acceptance output signal. Also,
specify whether to enable or disable the function for output of transfer-request-acceptance
signals from a pin.
AKSEn AKDEn
0 0
0 1
1 0
1 1
• Upon a reset, the bits in the register are initialized to 00.
• These bits can be read and written.
[Bits 17, 9, and 1] EPSEn
[Bits 16, 8, and 0] EPDEn
Specify the time at which to generate a transfer-end output signal. Also, specify whether to
enable or disable the function for outputting a transfer-end output signal from a pin.
EPSEn EPDEn
0 0
0 1
1 0
1 1
• Upon reset, the bits in the register are initialized to 00.
• These bits can be read and written.
Disables transfer-acceptance output.
Enables transfer-acceptance output during access to transfer
destination data.
Enables transfer-acceptance output during access to transfer
source data.
Enables transfer-acceptance output during access to transfer
destination data.
Disables transfer-end output.
Enables transfer-end output during access to transfer
destination data.
Enables transfer-end output during access to transfer source
data.
Enables transfer-end output during access to transfer source
and transfer destination data.
CHAPTER 17 DMA CONTROLLER
Description
Description
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