17.7.2 Timing charts for the data transfer section
This section covers timing charts for the data transfer section.
I Data transfer section, 16/8-bit data
❍ Transfer source area: External, Transfer destination area: External
(A)
CLK
DREQn
Addr pin
#2
Data pin
#2
RD
WRn
DACK
DEOP
❍ Transfer source area: External, Transfer destination area: Internal RAM
(A)
CLK
DREQn
Addr pin
#2
Data pin
#2
RD
WRn
DACK
DEOP
S
D
S
S
D
W
S
S
S
S
CHAPTER 17 DMA CONTROLLER
D
S
S
D
S
W
S
S
D
S
D
S
W
S
S
D
D
387