Gear Function - Fujitsu MB91150 Series Hardware Manual

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT

3.11.9 Gear Function

The gear function allows the elimination of some clock pulses from clock signals. It
has two independent circuits: A CPU and a peripheral circuit. These circuits allow the
exchange of data between the CPU and peripherals even when the gear ratio is
different. This function allows also to specify whether to use the same clock cycle as
that of the oscillation circuit or that from the divided-by-2 circuit.
I Block diagram of the gear control block
Figure 3.11-6 "Block diagram of the gear control block" shows a block diagram of the gear
control block.
Internal bus
Oscil-
X0
lation
X1
circuit
80
Figure 3.11-6 Block diagram of the gear control block
CCK
PCK
CHC
1/2
(Gradually doubled)
PLL
CPU system gear interval
indication signal
CPU clock system
gear interval
generation circuit
Peripheral clock
system gear
interval generation
circuit
Peripheral system gear
interval specification signal
CPU clock
Internal bus clock
Internal
peripheral clock