Fujitsu MB91150 Series Hardware Manual page 90

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
❍ [Bit 4] DBLON
This bit specifies the operation status of the clock doubler. It is initialized at reset.
DBLON
0
1
[Bits 3 and 2]: PCK1 and PCK0
These bits specify the peripheral system gear cycle. The relationship between these bits and
the cycle to be selected is shown below. These bits are initialized at reset.
PCK1
0
0
1
1
0
0
1
1
[Bit 0]: CHC
This bit specifies the divided-by-2 system or PLL system of the oscillation circuit as the basic
clock.
Setting this bit to 1 specifies the divided-by-2 system. Setting this bit to 0 specifies the PLL
system.
74
Internal operating frequency: same as external operating frequency
Operating in 1:1 relationship [Initial value]
Operating in 2:1 relationship
PCK0 CHC
0 0 PLL x 1
1 0 PLL x 1/2
0 0 PLL x 1/4
1 0 PLL x 1/8
0 1 Oscillation x 1/2
1 1 Oscillation x 1/2 x 1/2
0 1 Oscillation x 1/2 x 1/4
1 1 Oscillation x 1/2 x 1/8 [Initial value]
CPU machine clock (oscillation: input frequency
from X0)