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[Bit 15] PEN (Parity enable bit)
This bit selects whether to add a parity bit to serial data (for sending). This bit selects
whether to detect a parity bit (for receiving) within the serial data.
(Note) When operation mode 1 or 2 is selected, parity cannot be used. Always set this bit to
0.
[Bit 14] P (Parity selection bit)
This bit selects odd parity or even parity when parity is enabled (PEN = 1).
[Bit 13] SBL (Stop-bit-length selection bit)
This bit selects the bit length of the stop bit, which is a frame-end mark for the send data in
asynchronous transfer mode.
(Note) Only one bit is detected as stop bit at reception.
[Bit 12] CL (Data-length selection bit)
This bit specifies the data length of the send and receive data.
(Note) Bit 7 can be selected only in operation mode 0 (asynchronous). Bit 8 (CL = 1) must be
selected in operation mode 1 (multiprocessor mode) and operation mode 2 (synchronous).
[Bit 11] A/D (Address/data selection bit)
•
This bit specifies the data format of frames to be sent and received in multiprocessor mode
(mode 1).
•
When this bit is 0, ordinary data is selected. When this bit is 1, address data is selected.
[Bit 10] REC (Receive-error flag-clear bit)
•
This bit clears the FRE, ORE, and PE flags of the status register (SSR).
•
When this bit is set to 0, the FRE, ORE, and PE flags are cleared. When this bit is set to 1,
the flags do not change and other operations are not affected.
(Note) Clear the REC bit only when the FRE, DRE, or PE flag is 1 in receive interrupt
enabled status during UART operation.
[Bit 9] RXE (Receive-operation enable bit)
•
This bit controls the UART receive operation.
•
When this bit is 0, the receive operation is disabled. When this bit is 1, the receive operation
is enabled.
(Note) If the receive operation is disabled during reception, the receive operation stops when
reception of the frame is completed and receive data is stored in the receive data buffer
(SIDR0-3).
[Bit 8] TXE (Send-operation enable bit)
•
This bit controls the UART send operation.
•
When this bit is 0, the send operation is disabled. When this bit is 1, the send operation is
enabled.
(Note) If the send operation is disabled during sending, the send operation stops after the
send-data buffer (SODR0-3) runs out of data. When data is written to SODR0 to SODR3,
wait a specified period of time before setting this bit to "0". In clock asynchronous mode, this
specified period of time is 1/16 of the baud rate; in clock synchronous mode, it is the baud
rate.
CHAPTER 15 UART
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