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I Restrictions on branch instructions with delay slots
❍ Instructions that can be placed in delay slots
Only instructions that satisfy the following conditions can be executed in delay slots:
•
One-cycle instructions
•
Instructions other than branch instructions
•
Instructions that do not affect the operation although the execution order changes
A one-cycle instruction is indicated by writing 1, a, b, c, or d in the cycle count column of the
instruction list.
❍ Step trace trap
No step trace trap occurs between the execution of a branch instruction with the delay slot and
the delay slot.
❍ Interrupt and NMI
An interrupt and NMI are not accepted between the execution of a branch instruction with the
delay slot and the delay slot.
❍ Undefined instruction execution
No undefined instruction exception occurs if an undefined instruction exists in the delay slot. In
this case, the undefined instruction operates as the NOP instruction.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
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