Fujitsu MB91150 Series Hardware Manual page 288

32-bit microcontroller
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CHAPTER 12 INTERRUPT CONTROLLER
I Hold-request cancellation-request sequence
❍ Example for the interrupt routine
Figure 12.7-2 "Sample timing chart of the hold request cancellation-request sequence (Interrupt
level is HRCL > a)" is a sample timing chart of the hold request cancellation-request sequence
(interrupt level HRCL > a).
Figure 12.7-2 Sample timing chart of the hold request cancellation-request sequence
CPU
DHRQ
HRQ
HACK
IRQ
LEVEL
HRCR
PDRR
272
(Interrupt level is HRCL > a)
RUN
Bus hold
(1)(2)
a
0000
Interrupt handling
Bus hold (DMA transfer)
(3) (4)
0001
0000

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