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CHAPTER 15 UART
15.9.1 Operation in asynchronous mode (operation modes 0 to 1)
When the UART is used in operation mode 0 (normal mode) or operation mode 1
(multiprocessor mode), the transfer becomes asynchronous.
I Operation in asynchronous mode
❍ Transfer-data format
Transfer data always starts from the start bit (L level), is transferred LSB first with the specified
data bit length, and ends with the stop bit (H level).
•
In operation mode 0, data has either a fixed length of eight bits without parity or a fixed
length of 8 bits with parity.
•
In operation mode 1, data has a fixed length of eight bits without parity, but an address/data
selection bit (A/D) is added instead of the parity bit.
Figure 15.9-1 "Transfer-data format (operation modes 0 to 1)" shows the data format in
asynchronous mode.
Figure 15.9-1 Transfer-data format (operation modes 0 to 1)
[Operation mode 0]
[Operation mode 1]
*: D7 (bit 7): Without parity
P (parity): With parity
ST: Start bit
SP: Stop bit
A/D: Operation mode 1 (multiprocessor mode) address/data selection bit
❍ Send operation
When the send data empty flag bit (SSR0-3: TDRE) is 1, send data is written to the output-data
register (SODR0-3). If sending is enabled (SCR0-3: TXE = 1), the data is sent.
The send data is transferred to the send-shift register. When sending begins, the TDRE flag is
set to 1 again and setting of the next unit of send data is enabled. If send-interrupt requests are
enabled (SSR0-3: TIE = 1), a send-interrupt request that requests the send data to be set in
SODR0-3 is output. As soon as the send data is written to SODR0-3, the TDRE flag is cleared
to 0.
❍ Receive operation
If receiving is enabled (SCR0-3: RXE = 1), receive operations are consistently performed. When
the start bit is detected, data of one frame is received in accordance with the data format
determined by the control register (SCR0-3). After reception of the data of one frame, if an error
has occurred, the error flag is set and the receive data full flag bit (SSR0-3: RDRF) is set to 1. If
receive-interrupt requests are enabled (SSR0-3: RIE = 1), a receive-interrupt request is output.
Check each flag of the status register (SSR0-3). If reception is normal, read the input-data
336
ST
D0
D1
D2
ST
D0
D1
D2
D3
D4
D5
D6
D3
D4
D5
D6
*
D7/P
SP
D7
A/D
SP
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