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CHAPTER 17 DMA CONTROLLER
17.7 Timing Charts for the DMA Controller
This section covers timing charts for DMA controller operation.
• Timing chart for the descriptor access section
• Timing chart for the data transfer section
• Timing chart for transfer termination in continuous transfer mode
• Timing chart for transfer-end operation
I Symbols used in the timing charts
Table 17.7-1 Symbols used in the timing charts
Symbol
#0
#0H
#0L
#1
#1H
#1L
#2
#2H
#2L
#1/2
#1/2H
#1/2L
SH
SL
DH
DL
384
Descriptor No. 0
Bits 31 to 16 in descriptor No. 0
Bits 15 to 0 in descriptor No. 0
Descriptor No. 1
Bits 31 to 16 in descriptor No. 1
Bits 15 to 0 in descriptor No. 1
Descriptor No. 2
Bits 31 to 16 in descriptor No. 2
Bits 15 to 0 in descriptor No. 2
Descriptor No. 1 or No. 2 (Depending on SCS1 and 0, and DSC1 and 0)
Bits 31 to 16 in descriptor No. 1 or No. 2
Bits 15 to 0 in descriptor No. 1 or No. 2
S
Transfer source
Bits 31 to 16 of the transfer source
Bits 15 to 0 of the transfer source
D
Transfer destination
Bits 31 to 16 of the transfer destination
Bits 15 to 0 of the transfer destination
Description
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