Table of Contents
Advertisement
3.5
Word Alignment
Instructions and data are accessed in units of bytes. The address structure depends
on the instruction length and data length.
I Program access
An FR program must be located at an address that is a multiple of 2. Bit 0 of the PC is set to 0
when the PC is updated during instruction execution. Bit 0 of the PC may be set to 1 only when
an odd address is specified as a branch destination address. However, bit 0 is invalid in this
case, and the instruction must be placed at an even address.
There is exception allowing odd addresses.
I Data access
For data access, the FR series performs the following forcible alignment of addresses in
accordance with the bandwidth for data access:
Word access: Addresses are a multiple of 4 (the lower two bits are forcibly set to 00.)
Half word access: Addresses are a multiple of 2 (the lowest bit is forcibly set to 0.)
Byte access: -
At word or half word data access, some bits are forcibly set to 0 for calculating the effective
address. For example, in the addressing mode of @ (R13, Ri), the register value before addition
is used for calculation (even if the LSB is 1) and the lower bits of the addition result are masked.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
[Example] LD @ (R13, R2), R0
R13
R2
+ )
Addition result
Address pin
00002224
00002222
H
00000003
H
00002225
H
Lower two bits forcibly masked
H
45
Advertisement
Table of Contents
