Block Diagrams - Fujitsu MB91150 Series Hardware Manual

1.2

Block Diagrams

This section provides MB91150 block diagrams separately for individual packages.
I Block diagram for MB91FV150, MB91F155A and MB91155
Figure 1.2-1 "Block diagram (MB91FV150, MB91F155A and MB91155)" is a block diagram for
the MB91FV150, MB91F155A and MB91155.
Figure 1.2-1 Block diagram (MB91FV150, MB91F155A and MB91155)
P37/D31(IO)
P30/D24
DATA
P27/D23
P20/D16
P67/A23(O)
P60/A16
P57/A15
Address
P50/A8
P47/A7
P40/A0
P86/CLK(O)
P85/WR1(O)
Bus P84/WR0
Control P83/RD(O)
P82/BRQ(I)
P81/BGRNT(O)
P80/RDY(I)
PL7/DACK2
PL6/DREQ2
PL5/DEOP1
PL4/DACK1
DMAC
PL3/DREQ1
PL2/DEOP0(O)
PL1/DACK0(O)
PL0/DREQ0(I)
X0 (I)
Clock
X1 (I)
A/D PD7/INT15/ATG(I)
DMAC
PD6/INT14/DEOP2
PD5/INT13/ZIN1
PD4/INT12/ZIN0
PD3/INT11/BIN1
Up/Down
PD2/INT10/AIN1
Counter
PD1/INT9/BIN0(I)
PD0/INT8/AIN0(I)
External
PC7/INT7/CS3
Interrupt
PC6/INT6/CS2
PC5/INT5/CS1
PC4/INT4/CS0
PC3/INT3
PC2/INT2
PC1/INT1
PC0/INT0(I)
M
O
MD0
D
FR30 CPU Core
MD1 E
MD2 I-Bus
(4)
RST
P
O
R
T
3
/
2
(16)
P
O
R
T
6
/
5
/
4
(24)
I-Bus
P
O
R
External
T
Bus CTL
8
(7)
RAM
2KB
P
O
R
T
ROM
L
510KB
(8)
OSC Clock
(2)
Control
P
O
Interrupt
R
T
Controller
D
(8)
8bit
Up/Down
P
2ch
O
R
T
External
C
2
I C Interface
Interrupt
16ch
(8)
CHAPTER 1 OVERVIEW OF THE MB91150
D-Bus
Calendar
Data RAM
32KB
DMAC 8ch
Bit Search
D-Bus R-Bus
D-Bus
UART 4ch
C-Bus
UTIMER 4ch
16bit
Reload Timer
4ch
16bit
Free RUN Timer
1ch
16bit PPG
6ch
16bit
Input Capture
4ch
16bit
Output Compare
8ch
10bit 8input
A/D converter
Counter
8bit 3output
D/A converter
2
I C Interface
1ch
1ch
X0A
OSC
Clock
X1A
(2)
PE7/OC7
PE6/OC6
P
PE5/OC5
O
PE4/OC4 Output
R
T
PE3/OC3 Compare
PE2/OC2
E
PE1/OC1
(8)
PE0/OC0
PG5/PPG5
P
PG4/PPG4
O
R
PG3/PPG3
T
PPG
PG2/PPG2
G
PG1/PPG1
(6)
PG0/PPG0
PH0/SIN0
P
PH1/SOT0
O
R
PH2/SCK0/T00
T
PH3/SIN1
H
PH4/SOT1
(6)
PH5/SCK1/T01
UART
TOX:
PI0/SIN2
P
PI1/SOT2 Reload
O
R
Timer
PI2/SCK2/T02
T
PI3/SIN3
I
PI4/SOT3
(6)
PI5/SCK3/T03
P
O
PJ0/SCL
R
2
I C
T
PJ1/SDA
J
(2)
PK0/AN0
PK1/AN1
P
O
PK2/AN2
R
T PK3/AN3
A/D
PK4/AN4
K
PK5/AN5
(8)
PK6/AN6
PK7/AN7
P
PF4
O
R
PF3/IN3
T
PF2/IN2
Input
F
PF1/IN1
Capture
PF0/IN0
(5)
DA2
D
A
DA1
DA0
(3)
5