Fujitsu MB91150 Series Hardware Manual page 247

I Timer control status register (TCCS)
The register configuration of the timer control register (TCCS) is as follows:
Upper 8 bits of timer
control register
Lower 8 bits of timer
control register
[Bit 15]: ECLK
This bit is always set to 0 by the write processing.
0
1
[Bits 14 to 8]: Unused bits
[Bit 7]: IVF
This bit is an interrupt request flag of the 16-bit free-run timer. When an overflow occurs in
the 16-bit free-run timer, this bit is set to 1. If an interrupt request permission bit (bit 6: IVFE)
is set, an interrupt occurs. This bit is cleared by setting it to 1. Writing 1 has no effect. The
reading result of read modify write instructions is always 1.
0
1
[Bit 6]: IVFE
This bit is an interrupt permission bit for the 16-bit free-run timer. When this bit is 1 and the
interrupt flag (bit 7: IVF) is set to 1, an interrupt occurs.
0
1
Bit15 Bit14 Bit13
ECLK
R/W
(0) ( ) ( )
Bit7 Bit6 Bit5
IVF IVFE STOP
R/W R/W R/W
(0) (0) (0)
Internal clock source is selected (initial value).
Setting is prohibited.
No interrupt request (initial value)
Interrupt request
Prohibits an interrupt (initial value)
Allows an interrupt.
CHAPTER 9 MULTIFUNCTIONAL TIMER
Bit12 Bit11 Bit10
( ) ( ) ( )
Bit4 Bit3 Bit2
MODE SCLR CLK2
R/W R/W R/W
(0) (0) (0)
Bit9 Bit8
( ) ( )
Bit1 Bit0
CLK1 CLK0
R/W R/W
(0) (0)
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