Timing Charts For The Descriptor Access Section - Fujitsu MB91150 Series Hardware Manual

17.7.1 Timing charts for the descriptor access section

This section covers the timing charts for the descriptor access section.
I Descriptor access section
❍ Request pin input mode: Level, Descriptor address: External
CLK
DREQn
Addr pin
Data pin
RD
WRn
DACK
DEOP
❍ Request pin input mode: Level, Descriptor address: Internal
Internal KB
CLK
DREQn
Addr pin
Data pin
RD
WRn
DACK
DEOP
#0H #0L #1H
#0H #0L
(A)
S
S
CHAPTER 17 DMA CONTROLLER
#1L #2H
#1H #1L #2H
(A)
#2L S
#2L S
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