Fujitsu MB91150 Series Hardware Manual page 335

the TDRE bit is 1, the next send data can be written. If send-interrupt request output is enabled,
a send interrupt occurs. The next send data should be written when a send interrupt occurs or
when the TDRE bit is 1.
Note:
The SODR0-3 is a write-only register and the SIDR0-3 is a read-only register. The write
value and read value are different because these registers are located at the same address.
Therefore, instructions that perform the read-modify-write (RMW) operation cannot be used.
CHAPTER 15 UART
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