Fujitsu MB91150 Series Hardware Manual page 57

I Program counter (PC)
This register indicates the address of the instruction being executed. Bit 0 is set to 0 when
updating the PC during instruction execution.
Bit 0 may be set to 1 only when an odd address is specified as a branch destination address.
However, bit 0 is invalid in this case, and the instruction must be placed at an address that is a
multiple of 2.
The initial value at reset is undefined.
I Table base register (TBR)
This register stores the starting address of the vector table used for EIT processing. The initial
value at reset is 000FFC00
I Return pointer (RP)
This register stores the address for return from a subroutine. When the CALL instruction is
executed, a PC value is transferred to this register. When the RET instruction is executed, the
content of the RP is transferred to the PC.
The initial value at reset is undefined.
CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
31
PC
PC
31
TBR
TBR
.
H
31
RP
RP
[Initial value]
0
XXXXXXX
H
[Initial value]
0
000FFC00
H
[Initial value]
0
XXXXXXXX
H
41