Fujitsu MB91150 Series Hardware Manual page 127

(The pins function as I/O ports.) (Initial value)
• 1: BRQ input enabled, BGRNT output allowed
[Bit 6]: ClocK output Enable bit (CKE)
This bit enables output of the CLK (external bus operating clock pulse)
• 0: Output inhibited
• 1: Output allowed (initial value)
This bit is initialized to 1 when the system is reset and output of the CLK is allowed.
[Bits 5, 4]
These bits are not used. Writing to these bits has no effect.
The default value is 1.
[Bit 3]: Chip select Output Enable (COE3)
COE3 controls CS3 output.
Output is enabled after resetting.
• 0: Output prohibited
• 1: Output allowed (initial value)
[Bit 2]: Chip select Output Enable (COE2)
COE2 controls CS2 output.
Output is enabled after resetting.
• 0: Output prohibited
• 1: Output allowed (initial value)
[Bit 1]: Chip select Output Enable (COE1)
COE1 controls CS1 output.
Output is enabled after resetting.
• 0: Output prohibited
• 1: Output allowed (initial value)
[Bit 0]: Chip select Output Enable (COE0)
COE0 controls CS0 output.
Output is enabled after resetting.
• 0: Output prohibited
• 1: Output allowed (initial value)
In this model, keep this bit set to 1.
CHAPTER 4 BUS INTERFACE
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