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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
I Mode data
The data written at "0000 07FF
A mode register (MODR) is allocated at "0000 07FF
system runs in the mode specified by this register. Data can be written to the mode register only
once after resetting.
The setting in this register becomes effective immediately.
MODR
Address
: 0000 07FF
H
[Bits 7, 6] M1, M0
These bits set the bus mode. Specify the bus mode to be used after mode register writing.
M1
0
0
1
1
[Bits 5-0] *
These bits are reserved for the system.
Keep these bits set to 0.
❍ Notes on writing to MODR
Before writing to MODR, be sure to set AMD0-5 to decide the bus width of each Chip Select
(CS) area.
MODR has no bits for setting the bus width.
As for bus width, the value set for mode pins MD2 to MD0 is effective before MDR writing, and
the value set in BW1 and BW0 of AMD0-5 is effective after MODR writing.
For instance, an external reset vector is normally handled in Area 0 (in which CS0 is active) and
the bus width is determined by mode pins MD2 to MD0. Suppose MD2 to MD0 are set to
determine the bus width as 32 or 16 bits, while nothing is set in AMD0 (default bus width of 8
bits). If MODR is written under this condition, area 0 enters 8-bit bus mode, which results in a
malfunction.
To prevent this problem, always set AMD0-5 before writing to MODR.
66
" by the CPU after a reset is called mode data.
H
M1
M0
*
M0
0
Single chip mode
1
Internal ROM external bus mode
0
External ROM external bus mode
1
-
RST (reset)
Bus width specification: MD2, 1, 0
". After data is set in this register, the
H
*
*
*
Bus mode setting bits
Function
MODR writing
→
BW1, 0 of AMD0-5
Initial value Access
XXXXXXXX
*
*
Remarks
This setting is not allowed
W
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