Fujitsu MB91150 Series Hardware Manual page 78

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
I Operation for step trace trap
If the T flag in SCR of the PS is set and the step trace function is enabled, a trap occurs and a
break in processing occurs each time one instruction is executed.
❍ The conditions for detecting a step trace trap are as follows:
1. T flag = 1
2. The instruction in execution is not a delayed branch instruction
3. An operation other than execution of the INTE instruction or the step trace trap processing
routine is being executed.
4. When the above conditions are met, a processing break occurs at a pause in operation for
the instruction.
❍ Operation
Each item in parentheses in 1. to 7. below shows the address indicated by the register.
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the next instruction --> (SSP)
5. 00100 --> (SSP)
6. 0 --> S flag
7. (TBR + 3CCH) --> PC
When the T flag is set and the step trace trap is enabled, both user NMI and user interrupt are
disabled.
No EIT is generated by the INTE instruction in this case.
I Operation for an undefined instruction exception
If an undefined instruction is detected at instruction decoding, an undefined instruction
exception occurs.
❍ The conditions for detecting the undefined instruction exception are as follows:
1. An undefined instruction is detected at instruction decoding.
2. The instruction is located outside the delay slot (not immediately after the delayed branch
instruction).
3. When the above conditions are met, an undefined instruction exception occurs, causing a
break.
❍ Operation
Each item in parentheses in 1. to 6. below shows the address indicated by the register.
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. PC --> (SSP)
5. 0 --> S flag
6. (TBR + 3C4H) --> PC
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