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CHAPTER 17 DMA CONTROLLER
17.6 Notes on the DMA Controller
This section provides notes on using the DMA controller.
I Priority of channels
Once the DMAC is activated by a DMA transfer request over a channel, a DMA transfer request
over another channel is not accepted and is held until the end of the current transfer.
If requests over multiple channels are active at detection of a DMA transfer request by the
DMAC, which channel is to be accepted depends on the priority given below.
(High) ch 0 --> ch 1 --> ch 2 --> ch 3 --> ch 4 --> ch 5 --> ch 6 --> ch 7 (Low)
If requests over multiple channels are generated concurrently, the DMA transfer over one
channel is executed, then bus control is returned to the CPU before performing DMA transfer
over the next channel.
I Notes on using a resource interrupt request as a DMA transfer request
For DMA controller transfer, you must disable the interrupt levels via the appropriate interrupt
controller.
In contrast, for interrupt generation, you must disable the DMA controller operation enable bit in
the DMA controller and set the interrupt level to a proper value.
I Suppression of DMA transfer upon generation of a higher-priority interrupt
The FR supports a function for terminating DMA transfer originating in a DMA transfer request
when a higher-priority interrupt occurs.
❍ HRCL register
You can terminate DMA transfer operation upon occurrence of an interrupt request by operating
the HRCL (hold request cancel level register) in the interrupt controller.
If the interrupt level set in an interrupt request generated from a peripheral circuit is higher than
that set in the HRCL, DMAC DMA transfer operation is suppressed. With DMA transfer
operation executed, the transfer operation is suspended at a breakpoint, and the bus right is
given to the CPU. If the system is currently waiting for the generation of a DMA transfer request,
a DMA transfer request is held when it is generated.
After reset, the HRCL is set to the lowest level (31). The DMA transfer operation is, therefore,
suppressed against all interrupt requests. To operate DMA transfer even with an interrupt
request generated, set the HRCL register to the required value.
❍ PDRR register
The function for suppressing DMA transfer operation by setting the HRCL register is enabled
only when an interrupt request of a higher priority is active. For example, when an interrupt
request is cleared in the interrupt handler program, the suppression of DMA transfer by the
HRCL register may be released, with the CPU losing the bus right.
The clock control section supports a PDRR register to clear an interrupt request so that other
interrupt requests may be accepted, and to suppress DMA transfer operation.
If you use the interrupt handler to load the PDRR with a value other than 0, DMA transfer
operation is suppressed. To release the suppression of DMA transfer operation, load the PDRR
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