Priority Evaluation - Fujitsu MB91150 Series Hardware Manual

12.4 Priority Evaluation

This module selects the interrupt source with the highest priority, out of all interrupt
sources that occur at the same time, and outputs the interrupt level and interrupt
number of the source to the CPU.
I Priority evaluation
The criteria for evaluating the priority are shown below.
1. NMI
2. The interrupt source meets the following conditions:
• The interrupt source has an interrupt level other than 31 (A value of 31 represents interrupt
disable.)
• The interrupt source has the lowest interrupt level
• The interrupt source has the smallest interrupt number
Table 12.4-1 "Relationship between interrupt sources, interrupt numbers, and interrupt levels"
shows the relationship between interrupt sources, interrupt numbers, and interrupt levels.
Table 12.4-1 Relationship between interrupt sources, interrupt numbers, and interrupt
levels
Interrupt source
(NMI request)
External interrupt 0
External interrupt 1
External interrupt 2
External interrupt 3
External interrupt 4
External interrupt 5
External interrupt 6
External interrupt 7
External interrupt 8 to 15
UART0 (Receiving completed)
UART1 (Receiving completed)
UART2 (Receiving completed)
UART3 (Receiving completed)
UART0 (Sending completed)
UART1 (Sending completed)
UART2 (Sending completed)
Interrupt number
Decimal Hexadecimal
15 0F
16 10
17 11
18 12
19 13
20 14
21 15
22 16
23 17
24 18
26 1A
27 1B
28 1C
29 1D
31 1F
32 20
33 21
CHAPTER 12 INTERRUPT CONTROLLER
Interrupt Offset
level
15(F ) 3C0
H H
ICR00 3BC
H
ICR01 3B8
H
ICR02 3B4
H
ICR03 3B0
H
ICR04 3AC
H
ICR05 3A8
H
ICR06 3A4
H
ICR07 3A0
H
ICR08 39C
H
ICR10 394
H
ICR11 390
H
ICR12 38C
H
ICR13 388
H
ICR15 380
H
ICR16 37C
H
ICR17 378
H
TBR default
address
000FFFC0
H
000FFFBC
H
000FFFB8
H
000FFFB4
H
000FFFB0
H
000FFFAC
H
000FFFA8
H
000FFFA4
H
000FFFA0
H
000FFF9C
H
000FFF94
H
000FFF90
H
000FFF8C
H
000FFF88
H
000FFF80
H
000FFF7C
H
000FFF78
H
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