Retaining A Reset Source - Fujitsu MB91150 Series Hardware Manual

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT

3.11.10 Retaining a Reset Source

The system stores the last generated reset source. All related flags are set to 0 during
a read access.
A source flag that was set remains as long as it is not read.
I Block diagram of the reset source retention circuit
Figure 3.11-8 "Block diagram of the reset source retention circuit" shows the block diagram of
the reset source retention circuit.
Figure 3.11-8 Block diagram of the reset source retention circuit
Power-on detection
I Setting
No special setting is required to use this function. Set the instruction for reading the reset source
register and the instruction for branching to an appropriate program at the beginning of the
program to be stored at the reset entry address.
[Example]
RESET-ENTRY
LDI:32 #RSRR,R10
LDI:8
LDUB
MOV
AND
BNE
LSR
MOV
AND
BNE
...
82
watch-dog Timer
reset detect Circuit
RST pin
Reset input circuit
#10000000B,R2
@R10,R1 ; GET RSRR VALUE INTO R1
R1,R10 ; R10 USED AS A TEMPORARY REGISTER
R2,R10 ; WAS PONR RESET?
PONR-RESET
#1,R2 ; POINT NEXT BIT
R1,R10 ; R10 USED AS A TEMPORARY REGISTER
R2,R10 ; WAS WATCH DOG RESET?
WDOG-RESET
PONR
WDOG
ERST
SRST
decoder
Status
transition
circuit
.or.
PONR
WDOG
ERST
SRST
SRST