Fujitsu MB91150 Series Hardware Manual page 302

32-bit microcontroller
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CHAPTER 13 8/10-BIT A/D CONVERTER
[Bit 7, 6] MD1, MD0 (A/D conversion mode selection bits)
These bits are used for selecting the A/D conversion mode.
Single-conversion mode 1, single-conversion mode 2, continuous-conversion mode, or
intermittent-conversion mode is selected in accordance with the values in the MD1 and MD0
bits.
The operation in each mode is as follows:
Single-conversion mode 1: Consecutively performs A/D conversion between the channel
specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0 only once. The
converter can be restarted.
Single-conversion mode 2: Consecutively performs A/D conversion between the channel
specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0 only once. The
converter cannot be restarted.
Continuous-conversion mode: Repeatedly performs A/D conversion between the channel
specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0 until operation is
forcibly stopped with the BUSY bit. The converter cannot be restarted.
Intermittent-conversion mode: Repeatedly performs A/D conversion between the channel
specified by ANS2 to ANS0 and the channel specified by ANE2 to ANE0, temporarily
stopping A/D conversion on a per-channel basis, until it is forcibly stopped by the BUSY
bit. The converter cannot be restarted. A temporarily stopped A/D conversion is restarted
in accordance with the start source selected with the STS1 and STS0 bits.
(Note)
When the converter cannot be restarted in single-, continuous-, or intermittent-conversion
modes, the converter cannot be restarted by the timer, external trigger or software.
[Bit 5, 4, 3] ANS2, ANS1, ANS0 (A/D conversion start channel selection bits)
These bits are used to specify the channel on which A/D conversion starts, and for checking
the number of the channel on which conversion is being performed.
The converter starts A/D conversion from the channel specified by these bits.
The number of the channel on which conversion is being performed can be read during A/D
conversion. While A/D conversion is being temporarily stopped in intermittent-conversion
mode, the number of the channel for which conversion was previously performed can be
read.
[Bit 2, 1, 0] ANE2, ANE1, ANE0(A/D conversion end channel selection bits)
These bits specify the channel at which A/D conversion ends.
A/D conversion is performed up to the channel specified by these bits at the start of A/D
conversion.
When the channel specified by ANS2 through ANS0 is specified by these bits, A/D
conversion is performed only for this channel.
When continuous-conversion mode or intermittent-conversion mode is specified, A/D
conversion control returns to the start channel specified by ANS2 to ANS0 after A/D
conversion is performed for the channel specified by these bits. When the specified start
channel number is larger than the specified end channel number, conversion is performed
from the start channel to AN7, then from AN0 to the end channel in a cycle.
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