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CHAPTER 4 BUS INTERFACE
4.1
Outline of Bus Interface
The bus interface controls the interface with external memory and external I/O units.
I Bus interface features
•
24-bit (16MB) address output
•
A bus width of 16 or 8-bit can be specified
•
Programmable automatic memory wait (up to seven cycles)
•
Support of little-endian mode
•
Unused addresses and data pins can be used as I/O ports
•
Use of an external bus exceeding 25 MHz is prohibited.
•
When a clock doubler is used, the bus speed is half the CPU speed.
I Area
Six types of chip select areas are provided in the bus interface.
Each area can be allocated as desired in minimum units of 64 KB in a 4 GB space by using the
area select registers (ASR1 to ASR5) and area mask registers (AMR1 to AMR5).
Note:
Area 0 is allocated in a space other than the areas specified by ASR1 to ASR5. When the
system is reset, area 0 is allocated in an external area other than 00010000
(This model uses only four chip select output pins of chip select areas 0 to 3.)
Figure 4.1-1 "Examples of Allocating Chip Select Areas" (a) shows an example of allocating
areas 1 to 5 in units of 64 KB from 00100000H to 0014FFFFH. Figure 4.1-1 "Examples of
Allocating Chip Select Areas" (b) shows an example of allocating area 1 of 512 KB from
00000000H to 0007FFFFH and areas 2 to 5 in units of 1 MB from 00100000H to 004FFFFFH.
98
to 0005FFFF
.
H
H
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