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CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
I Internal architecture
The FR CPU uses the Harvard architecture in which the instruction bus and data bus are
mutually independent.
The bus converter for 32 bits <--> 16 bits is connected to the data bus (D-BUS) to provide the
interface between the CPU and peripheral resources.
The bus converter for Harvard <--> Princeton is connected to both I-BUS and D-BUS to provide
the interface between the CPU and bus controller.
Figure 3.2-1 "Internal architecture" shows the internal architecture of the device.
3 2 b i t
1 6 b i t
Bus-Converter
R-bus
Resource
❍ CPU
The FR architecture of 32-bit RISC is compactly implemented in the CPU of this product. The
CPU uses the 5-stage instruction pipeline method to execute one instruction per cycle. The
pipeline consists of the following stages:
•
Instruction fetch (IF): Outputs an instruction address and fetches the instruction.
•
Instruction decode (ID): Decodes the fetched instruction. Also reads a register.
•
Execution (EX): Executes arithmetic operations.
•
Memory access (MA): Accesses the memory (loads or stores data in the memory).
•
Write back (WB): Writes the arithmetic operation results (or loaded memory data) to the
register.
Figure 3.2-2 "Instruction pipeline" shows the instruction pipeline.
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Figure 3.2-1 Internal architecture
F R
C P U
D-BUS
I-BUS
Harvard
Princeton
Bus-Converter
C-bus
Bus-Controller
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