Eit Operation - Fujitsu MB91150 Series Hardware Manual

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT
3.8.5

EIT Operation

This section describes EIT operation.
Assume that the PC of the transfer source in the explanation below indicates the
address of the instruction for which an EIT source was detected.
"Address of the next instruction" means that the instruction for which EIT was
detected satisfies the following conditions:
• LDI:32: PC + 6
• LDI:20, COPOP, COPLD, COPST, and COPSV: PC + 4
• Other instructions: PC + 2
I User interrupt operation
If a user interrupt request occurs, the system determines whether the request can be accepted
in the following order:
❍ Determination of whether the interrupt request can be accepted
1. The interrupt levels of concurrent requests are compared with each other. The request with
the highest level (smallest value) is selected. For an interrupt that can be masked, the value
stored by the associated ICR is used as the level for comparison.
2. If two or more interrupt requests with the same level occur, the interrupt request having the
smallest number is selected.
3. The interrupt level of the selected interrupt request is compared with the level mask value
determined by the ILM.
• In case the interrupt level is equal to or greater than the level mask value, the interrupt
request is masked and is not accepted.
• If the interrupt level is smaller than the level mask value, the system proceeds with step 4.
4. When the selected interrupt request can be masked and the I flag is 0, the interrupt request
is masked and is not accepted.
• If the I flag is 1, the system proceeds with step 5.
5. When the above condition is met, the interrupt request is accepted at a pause of instruction
processing.
❍ Operation
When a user interrupt request is accepted at EIT request detection, the CPU operates as shown
below while using the interrupt number associated with the accepted interrupt request.
The items in parentheses in 1. to 7. below show the address indicated by the register.
1. SSP-4 --> SSP
2. PS --> (SSP)
3. SSP-4 --> SSP
4. Address of the next instruction --> (SSP)
5. Interrupt level of the accepted request --> ILM
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