Write Cycle In Each Mode - Fujitsu MB91150 Series Hardware Manual

CHAPTER 4 BUS INTERFACE
4.5.4

Write Cycle in Each Mode

Figure 4.5-8 "Sample write cycle timing chart 1" to Figure 4.5-12 "Sample write cycle
timing chart 5" show examples of the write cycle timing in each mode.
I Write cycle timing in each mode
❍ Bus width: 16 bits Access: In units of words
❍ Bus width: 16 bits Access: In units of half words
❍ Bus width: 16 bits Access: In units of bytes
BA1
CLK
A23-00 #0
D31-24
#0
D23-16
X
WR0
WR1
138
Figure 4.5-8 Sample write cycle timing chart 1
BA1
CLK
A23-00 #0
D31-24 #0
D23-16 #1
WR0
WR1
Figure 4.5-9 Sample write cycle timing chart 2
BA1 BA2
CLK
#0
A23-00
#0
D31-24
#1
D23-16
WR0
WR1
Figure 4.5-10 Sample write cycle timing chart 3
BA2 BA1 BA2
#1
X
#1
BA2 BA1 BA2
#2
#2
#3
BA1 BA2
#2
#2
#3
BA1 BA2
#2
#2
X
X: Output of invalid data
BA1 BA2
#3
X
#3