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CHAPTER 21 FLASH MEMORY
[Bit 0]: LPM (Low power mode)
Bit 0 is used to enable the function for decreasing power consumption other than through
flash access during low-speed operation.
Setting this bit to 1 prevents the flash memory circuit from being started when the address is
changed.
Use the function of this bit only when the CPU operating frequency is less than or equal to
10 MHz.
0
1
•
At reset, this bit is initialized to 0.
•
This bit can both be read and written.
Wait register (FWTC)
FWTC controls flash memory wait in CPU mode.
It also controls high-speed read (33 MHz operation) access of flash memory.
The configuration of the FWTC is as follows:
0007C4 h
[Bits 1 and 0]: WTC1 and WTC0
Bits 1 and 0 are used to control flash memory wait.
- 00: +0 wait, 2 cycles [initial value]
- 01: Cannot be used.
- 10: Cannot be used.
- 11: Cannot be used.
[Bit 2]: FACH
Bit 2 is used to control the flash macro read speed.
- 0: Reads flash macro at normal speed.
- 1: Reads flash macros at high speed (used in 33-MHz operation).
420
Normal status. CEX output becomes L regardless of whether flash memory is
accessed. [Initial value]
CXE output becomes L only when flash memory is accessed.
bit 7
bit 6
bit 5
bit 4
( )
( )
( )
( )
bit 3
bit 2
bit 1
bit 0
FACH
WTC1
WTC0
W
R/W
R/W
( )
(0)
(0)
(0)
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