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❍ Channel 1
Figure 6.2-2 "Block diagram of the 8/16-bit up/down counter/timer (channel 1)" shows a block
diagram of the 8/16-bit up/down counter/timer (for Channel 1).
Figure 6.2-2 Block diagram of the 8/16-bit up/down counter/timer (channel 1)
CGE1
CGE0
ZIN1
Detects edge or level
UDCC
CMS1
AIN1
Select up or down
counter clock
BIN1
Prescaler
CLKS
Data bus
8bit
RCR1 (Reload/compare register 1)
C/GS
RCUT
UCRE
Clear counter
8bit
UDCR1 (Up/down count register 1)
CMS0
CES1
CES0
Carry
UDF1
UDF0
CSTR
Output interrupt
CHAPTER 6 8/16-BIT UP/DOWN COUNTER/TIMER
Control reload
RLDE
UDFF
M16E
CITE
Count clock
CDCF
CFIE
CMPF
OVFF
UDIE
167
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