Dma Request Suppression Register (Pdrr) - Fujitsu MB91150 Series Hardware Manual

CHAPTER 3 MEMORY SPACE, CPU AND CONTROL UNIT

3.11.6 DMA Request Suppression Register (PDRR)

The DMA request suppression register temporarily suppresses a DMA request so as to
enable CPU operation.
I DMA request suppression register (PDRR)
The register is configured as follows:
PDRR
000482
[Bits 11 to 08]: D3 to D0
If these bits are set to a value other than 0, DMA transfer from subsequent DMAs to the CPU
is suppressed. Afterwards, DMA can be used only when these bits are set to 0.
Note:
Do not use the PDRR register alone. Be sure to use it together with HRCL.
76
15 14 13
- - -
( - ) ( - ) ( - )
12 11 10
-
D3 D2
( - ) (R/W) (R/W) (R/W)
9 8 Initial value
D1 D0 ——0000
( R/W)