Platform Power Delivery Requirements; Recommended; Recommended Platform Power Delivery - Intel Quark SoC X1000 Design Manual

Platform Power Delivery Requirements—Intel
14.0

Platform Power Delivery Requirements

This chapter provides the recommended way to power up the Intel
X1000 from the platform. It is assumed the platform provides a single input voltage
(5v) from which we derive three primary platform voltages (1.0v, 3.3v, and 1.5v). Each
of these primary platform voltages are split and subsequently enabled in a specific
sequence to ensure proper SoC functioning.
The platform power rails can be categorized based on S5, S3 and S0 power domains on
®
the Intel
Table 51.

Recommended Platform Power Delivery

Primary Platform
Voltage
3.3V
1.0V
1.5V
3.3V
1.0V
1.5V
3.3V
1.0V
1.5V
Notes:
1. RED: S5 power domain
2. GREEN: S3 power domain
3. BLUE: S0 power domain
4. SoC o/p: Output handshake signal from SoC
5. SoC i/p: Input handshake signal into the SoC
6. Internal PMU: On die power management unit
S5 is the first power domain to ramp up, then S3 and subsequently the S0 power
domain. 4 voltage levels exist within each power domain namely 3.3V, 1.5V, 1.8V and
1.0V. The 3.3V, 1.5V and 1.0V power rails are powered from an external power source
(External to the Quark X1000 SoC on the platform). 1.8V on all 3 power domains are
powered internally from on-die LDOs. V1P0_S3 is an exception which is powered from
an internal on-chip LDO.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
Quark™ SoC X1000.
Derivative
Voltage
V3P3_S5 Vin (5V)
V1P0_S5 Vin (5V)
V1P5_S5 Vin (5V)
V3P3_S3 V3P3_S5
V1P0_S3_IVR V3P3_S3
V1P5_S3 V1P5_S5
V3P3_S0 V3P3_S5
V1P0_S0 V1P0_S5
V1P5_S0 V1P5_S5
Derived from Controlled by
Platform Power up
Supply: V3P3_S5
Supply: V1P0_S5
SoC i/p: S5_PGOOD
SoC o/p: S3_3V3_EN
SoC internal PMU
SoC o/p: S3_1V5_EN
SoC i/p: S3_PGOOD
SoC o/p: S0_3V3_EN
SoC o/p: S0_1V0_EN
SoC i/p: PG_V1P0_S0
SoC o/p: S0_1V5_EN
SoC i/p: S0_PGOOD
®
Quark™ SoC
Power-up
Sequence
1
2
3
4
5
6
7
8
9
®
Intel Quark™ SoC X1000
PDG
97