Table of Contents
Advertisement
:Preparation for Use
2.4 USER FURNISHED COMPONENTS
A serial 1/0 connector (see ·table 2-1) and RS-232-C
cable must be installed to interface the processor
board to a CRT terminal.
2.5 .POWER REQUIREMENTS
The iSBC 432/ 100 board requires +5V, + l 2V, and
- l 2V power supplies at the currents listed in table
1-1.
2.6 COOLING REQUIREMENTS
The iSBC 432/100 board dissipates 336.5 gram-
calories/minute (1.33 BTU/minute), and adequate
circulation
must
be
provided
to
prevent
a
temperature rise above 50° C (122° F). Intellec
systems include fans to provide adequate intake and
exhaust of ventilating air.
iSBC 432/100
2.7 PHYSICAL DIMENSIONS
Physical dimensions of the iSBC 432/ 100 board are
as follows:
a.
Width: 30.48 cm (12.00 inches)
b.
Height: 17 .15 cm (6. 75 inches)
c.
Thickness: 1.52 cm (0.6 inch)
2.8 JUMPER CONFIGURATION
The iSBC 432/ 100 design includes a variety of
jumper-selectable options that allow the user to
configure the board for his/her particular applica-
tion. Table 2-2 summarizes these options and lists the
grid reference locations of the jumpers as shown in
figure 5-1 (parts location diagram) and figure 5-2
(schematic diagram).
Table 2-2. Jumper Selectable Options
Fig. 5-1
Fig. 5-2
Function
Grid Ref.
Grid Ref.
Description
1/0
Base Address
1B6
2C5
Selects the Multibus base address for on-board
1/0
ports. The
default jumper (79-80*) configures the
110
addresses to 1X. The
value of X is determined by the
1/0
port to be addressed (refer
to table 3-1 ). Other base addresses are selected as follows:
address
jumper
7X
67-68
6X
69-70
5X
71-72
4X
73-74
3X
75-76
2X
77-78
1X
79-80*
XACK/Timing
1B8
3A6
The factory default jumper 54-55* provides the correct XACK
delay to read and write on-board
1/0
ports. This jumper should
not be modified.
8/16-bit bus access
1B4
7C2
Selects 8- or 16-bit Multibus transfer mode. The default jumper
configuration (46-47*) selects the ·a-bit transfer mode. In this
I
mode, all Multibus accesses are single-byte accesses. By
jumpering 45-46, the 16-bit Multibus mode is selected.
Bus Lock
187
2A6
Default jumper 65-66* locks the Multibus bus during each GDP
data transfer. A GDP initiated data transfer may require as
many as ten Multibus transfers in the 8-bit mode. To allow
other masters to acquire the bus during GDP transfers, remove
this jumper and connect 64-65.
Processor ID
1C8
2C4
Default jumpr 33-34* permits the GOP to read its processor ID
from an on-board register at
1/0
address
OOH.
This jumper
should not be removed.
Interrupt Signals
1 B7
4D1
A board generated interrupt may be routed to one of the
Multibus interrupt lines (INT5/, INT6/, or INT?/). Default jumper
J
86-87* routes the interrupt signal to INT6/. If another interrupt
line is desired. remove this jumper and connect 88-89 (INT?/) or
90-91 (INT51).
-~
•Default jumper configured at the factory
2-2
Advertisement
Table of Contents
