Intel 855Gme Chipset Platform Power-Up Sequence; Gmch Power Sequencing Requirements; 6300Esb Power Sequencing Requirements; V5Ref/3.3V Sequencing - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
4.7

Intel 855GME Chipset Platform Power-Up Sequence

The following sections describe the power-on timing sequence for Intel 855GME chipset Graphics
Memory Controller Hub (82855GME) based platforms.
4.7.1

GMCH Power Sequencing Requirements

All GMCH power rails shall be stable before PWROK is asserted. The power rails may be brought
up in any order
come up as close in time as practical, with the core voltage (1.35 V) coming up first. RSTIN#,
which brings GMCH out of reset, shall be deasserted only after PWROK has been active for 1 ms.
After GMCH is out of reset, it deasserts CPURST# within 1 ms.
Figure 49. GMCH Power-up Sequence
CPURST#
RSTIN#
PWROK
GMCH PWR
Rails
4.7.2

6300ESB Power Sequencing Requirements

4.7.2.1 V /3.3V Sequencing
5REF
V5REF is the reference voltage for 5 V tolerance on inputs to the 6300ESB. V5REF must be
powered up before Vcc3_3, or after Vcc3_3 within 0.7 V. Also, V5REF must power down after
Vcc3_3, or before Vcc3_3 within 0.7 V. It must also power down after or simultaneous to Vcc3_3.
These rules must be followed to ensure the safety of the 6300ESB. If the rule is violated, internal
diodes will attempt to draw power sufficient to damage the diodes from the Vcc3_3 rail.
shows a sample implementation of how to satisfy the V5REF/3.3 V sequencing rule.
This rule also applies to V5REF_Sus and VccSus3_3. However, in most platforms, the VccSus3_3
rail is derived from the 5 VSB through a voltage regulator and therefore, the VccSus3_3 rail will
always come up after the VccSus5 rail. As a result, V5REF_Sus (which is derived directly from
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desired. However, good design practice would have all GMCH power rails
1ms min
January 2007
6300ESB ICH Embedded Platform Design Guide
1ms max
Figure 50
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