Table of Contents
Advertisement
26.0
Debug Port Design Guide
26.1
Overview
This chapter provides information about the design of an eXtended Debug Port (XDP).
The details of this chapter are requirements for debug port design, unless the text
explicitly states that a design rule or connection is optional.
Note:
The ITP-XDP and ITP-XDP2 are run-control tools created by Intel® Corporation. They
are not sold publicly by Intel. In this document, the term ITP and ITP-XDP can be
interchanged with "run-control tool." Intel works with several run-control tool vendors
to create tools that can be used for design (the guidelines presented within this
document must also be followed). These vendors include:
• American Arium*
• International Test Technologies*
• Antron Electronics*
26.2
Terms and Definitions
Table 94.
Terms and Definitions
BPM
Debug Port
EMTS
2
I
C
ITP
ITP-XDP
ITP-XDP2
JTAG
Local Tap Master
OCP
Power
Reset
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
258
®
Intel
EP80579 Integrated Processor Product Line—Debug Port Design Guide
Term
Break Point Monitor - Processor pins used by run-control tools to monitor and
influence the internal state of the processor
Connection into a processor/chipset/platform environment used to provide
control during debug and validation.
Electrical Mechanical Thermal Specification
Inter-IC Bus. A two-wire serial interface.
In-Target Probe. An ITP is a run-control tool as produced by Intel as well as
third party vendors. This specification is not meant to imply that any vendor's
debug tool is preferred over any other. Contact your Intel representative for
alternative vendors supporting the XDP.
A specific ITP for the eXtended Debug Port
Functionally identical to ITP-XDP with the single added feature. of a built in
USB power assist module.
Joint Test Access Group. IEEE Standard 1149.1 style scan chain.
A device other than the ITP that is designed to control accesses into an IEEE
Standard 1149.1 style scan chain and all TAP agents contained within that scan
chain.
Observation Control Port
Detection of and response to the system powergood state.
Detection and control of reset state for elements within the system.
Definition
Order Number: 320068-005US
May 2010
Advertisement
Table of Contents
