General Topology And Layout Guidelines; System Bus T-Topology; System Bus Timing Parameters; Sample Cpu To Cpu Flight Time Calculations - Intel Pentium III Processor 512K Design Manual

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LV Intel Pentium III Processor 512K Dual Processor Platform
Table 5.

System Bus Timing Parameters

Timing Term
T [ns]
skew
T [ns]
jit
T [ns]
adj
T [ns] (133 MHz)
cycle
Table 6 summarizes the flight time requirements for CPU to CPU transfers that result from using
the component timing specifications and recommended system timings. All component values
should be verified against the latest specifications before proceeding with analysis.
Table 6.

Sample CPU to CPU flight time calculations

Driver
CPU
CPU
3.2

General Topology and Layout Guidelines

Intel recommends that all LV Intel Pentium
system bus T-topology. Figure 4 shows a high level diagram of this topology. The pull-up resistors
shown inside the processor packages are the processor's on-die AGTL termination, since the LV
Intel Pentium
Figure 4. System Bus T-Topology
14
Receiver
CPU
CPU
processor 512K has on-die termination.
III
V
TT
R1
CPU0
RTTCTRL
R3
Value
0.25
0.20
0.50
7.50
Calculation
T >= 1.0 - 0.4 + 0.25 = 0.85 ns
flight,min
T <= 7.5 - 3.25 - 0.95 - 0.25 - 0.2 - 0.5 = 2.35 ns
flight,max
III processor 512K dual-processing platforms use a
L0 L1
Chipset
V
TT
R2
CPU1
RTTCTRL
R4
Design Guide