Tc_Rfp_C1-Refresh Parameters Register; Tc_Rftp_C1-Refresh Timing Parameters Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.14.2 TC_RFP_C1—Refresh Parameters Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
BIOS Optimal Default:
Bit
31:18
17:16
15:12
11:8
7:0
2.14.3 TC_RFTP_C1—Refresh Timing Parameters Register
B/D/F/Type:
Address Offset:
Default Value:
Access:
Size:
Bit
31:25
24:16
15:0
Datasheet, Volume 2
0/0/0/MCHBAR MC1
4694–4697h
0000980Fh
RW-L
32 bits
0000h
Reset RST/
Attr
Value PWR
RO 0h
RW-L 00b Uncore
RW-L 9h Uncore
RW-L 8h Uncore
RW-L 0Fh Uncore
0/0/0/MCHBAR MC1
4698–469Bh
46B41004h
RW-L
32 bits
Reset RST/
Attr
Value PWR
RW-L 23h Uncore
RW-L 0B4h Uncore
RW-L 1004h Uncore
Description
Reserved
Double Refresh Control (DOUBLE_REFRESH_CONTROL)
This field will allow the double self refresh enable/disable.
00b = Double refresh rate when DRAM is WARM/HOT.
01b = Force double self refresh regardless of temperature.
10b = Disable double self refresh regardless of temperature.
11b = Reserved
Refresh panic WM (Refresh_panic_wm)
tREFI count level in which the refresh priority is panic (default is 9)
It is recommended to set the panic WM at least to 9, in order to
use the maximum no-refresh period possible.
Refresh high priority WM (Refresh_HP_WM)
tREFI count level that turns the refresh priority to high (default is
8)
Rank idle timer for opportunistic refresh (OREF_RI)
Rank idle period that defines an opportunity for refresh, in DCLK
cycles
Description
9 * tREFI (tREFIx9)
Period of minimum between 9*tREFI and tRAS maximum (normally
70 us) in 1024 * DCLK cycles (default is 35) – need to reduce
100 DCLK cycles – uncertainty on timing of panic refresh.
Refresh execution time (tRFC)
Time of refresh from beginning of refresh until next ACT or refresh
is allowed (in DCLK cycles, default is 180)
tREFI period in DCLK cycles (tREFI)
This field defines the average period between refreshes, and the
rate that tREFI counter is incremented (in DCLK cycles, default is
4100)
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