Intel ® 80960Rm/Rn Processor Memory Subsystem; Rom, Sram, Or Flash Guidelines; Flash Interface Signals - Intel i960 Design Manual

Intel® i960® RM/RN I/O Processor
®
Intel 80960RM/RN Processor Memory Subsystem
4.0 Intel
Subsystem
The RM/RN I/O processor
RM/RN I/O processor
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Up to 16 Mbytes of 8-bit Flash, ROM, or SRAM
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Between 8 and 128 Mbytes of 64-bit synchronous DRAM (SDRAM)
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Between 4 and 64 Mbytes of 32-bit synchronous DRAM for low cost solutions
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Single-bit error correction, double-bit and nibble detection support (ECC)
The Flash interface provides an 8-bit data bus, 23-bit address bus, and control to support up to two
64 Mbit Bulk-Erase or Boot-Block Flash devices. The Flash devices provide storage for the
RM/RN I/O processor
The memory controller provides a separate SDRAM interface from the Flash interface. The SDRAM
interface consists of a 66 MHz, 64-bit wide data path to support 528 Mbytes/sec throughput. An 8-bit
Error Correction Code (ECC) across each 64-bit word improves system reliability.
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The memory controller supports two banks of SDRAM in the form of a single two-bank dual
inline memory module (DIMM) or two single-bank DIMMs.
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The memory controller supports a 32-bit SDRAM data interface. This mode enables
lower-cost solutions at the cost of system bandwidth.
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The memory controller responds to internal bus memory accesses within its programmed
address range and issues the memory request to either the Flash or SDRAM interface.
The memory controller provides four chip enables to the memory subsystem. Two chip enables
service the SDRAM subsystem (one per bank) and two service the Flash devices.
Note: If the design does not follow the listed guidelines, then it is very important that the design be
simulated. Even if the guidelines are followed it is still recommended that the design be simulated
for proper signal integrity, flight time, and cross talk.
4.1

ROM, SRAM, or Flash Guidelines

The RM/RN I/O processor
ranging from 64 Kbytes to 16 Mbytes. This memory may be SRAM, ROM, or Flash. Optionally,
one of the banks may be dedicated to a UART device.
Table 4-1.

Flash Interface Signals

Pin Name
RCE[1:0]#
RWE#
ROE#
RAD[16:0]
RALE
12
®
80960RM/RN Processor Memory
integrates a memory controller to provide a direct interface between the
and its local memory subsystem. The memory controller supports:
initialization code.
memory controller provides an interface to two banks of static memory
Chip Enable - Asserted for all transactions to the Flash device.
Write Enable - Controls the Flash input data buffers.
Output Enable - Asserted for reads, deasserted for writes. Controls the Flash output data
buffers for write transactions.
Address/Data bus - Capable of supporting 16 Mbit of Flash (2Mx8). The data bus is
multiplexed on RAD[16:9].
Address Latch Enable - Indicates the transfer of a physical address. RALE is asserted
during a Flash address cycle and deasserted before the beginning of the data cycle.
*
Table 4-1 defines all Flash interface signals.
Description
Design Guide