Fwh Guidelines; Fwh Decoupling; In Circuit Fwh Programming; Fwh Vpp Design Guidelines - Intel Pentium 4 Design Manual

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9.11

FWH Guidelines

9.11.1

FWH Decoupling

A 0.1 µF capacitor should be placed between the VCC supply pins and the VSS ground pins to
decouple high frequency noise, which may affect the programmability of the device. Additionally,
a 4.7 µF capacitor should be placed between the VCC supply pins and the VSS ground pins to
decouple low frequency noise. The capacitors should be placed no further than 390 mils from the
VCC supply pins.
9.11.2

In Circuit FWH Programming

All cycles destined for the FWH will appear on PCI. The ICH2 hub interface to PCI Bridge will
put all processor boot cycles out on PCI (before sending them out on the FWH interface). If the
ICH2 is set for subtractive decode, these boot cycles can be accepted by a positive decode agent
on the PCI bus. This enables the ability to boot from of a PCI card that positively decodes these
memory cycles. To boot from a PCI card, it is necessary to keep the ICH2 in subtractive decode
mode. If a PCI boot card is inserted and the ICH2 is programmed for positive decode, there will be
two devices positively decoding the same cycle. In systems with the 82380AB (ISA bridge), it is
also necessary to keep the NOGO signal asserted when booting from a PCI ROM. Note that it is
not possible to boot off a ROM behind the 82380AB. Once you have booted from the PCI card,
you could potentially program the FWH in circuit and program the ICH2 CMOS.
9.11.3

FWH Vpp Design Guidelines

The Vpp pin on the FWH is used for programming the flash cells. The FWH supports Vpp of
3.3 V or 12 V. If Vpp is 12 V the flash cells will program about 50% faster than at 3.3 V.
However, the FWH only supports 12 V Vpp for 80 hours. The 12 V Vpp would be useful in a
programmer environment, which is typically an event that occurs very infrequently (much less than
80 hours). The VPP pin MUST be tied to 3.3 V on the motherboard.
In some instances, it is desirable to program the FWH during assembly with the device soldered
down on the board. In order to decrease programming time it becomes necessary to apply 12 V to
the V pin. The following circuit will allow testers to put 12 V on the V
PP
voltage separated from the 3.3 V plane to which the rest of the power pins are connected. This
circuit also allows the board to operate with 3.3 V on this pin during normal operation.

Figure 133. FWH VPP Isolation Circuitry

® ®
Intel Pentium 4 Processor / Intel
3.3V 12V
1K
®
850 Chipset Family Platform Design Guide
PP
FET
VPP
I/O Controller Hub 2
pin while keeping this
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