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9.
AGP Port Design Guidelines
For detailed AGP interface functionality (e.g., protocols, rules, signaling mechanisms), refer to the latest
AGP Interface Specification, Revision 2.0, which can be obtained from http://www.agpforum.org. This
section focuses only on specific Intel 855GME chipset platform recommendations.
9.1.
AGP Interface
The AGP Interface Specification Revision 2.0 enhances the functionality of the original AGP Interface
Specification (revision 1.0) by allowing 4X data transfers (4 data samples per clock) and 1.5-volt
operation. In addition to these major enhancements, additional performance enhancement and
clarifications, such as fast write capability, are included in Revision 2.0 of the AGP Interface
Specification.
The 4X operation of the AGP interface provides for "quad-sampling" of the AGP AD (Address/Data)
and SBA (Side-band Addressing) buses. That is, the data is sampled four times during each 66-MHz
AGP clock. This means that each data cycle is ¼ of a 15 ns period (66-MHz clock) or 3.75 ns. It is
important to realize that 3.75 ns is the data cycle time, not the clock cycle time. During 2X operation,
the data is sampled twice during a 66-MHz clock cycle. Therefore, the data cycle time is 7.5 ns.
In order to allow for these high-speed data transfers, the AGP interface uses source synchronous data
strobing in 2X mode and differential source synchronous data strobing in 4X mode.
With data cycle times as small as 3.75 ns and setup/hold times of 1 ns, propagation delay mismatch is
critical. In addition to reducing propagation delay mismatch, it is important to minimize noise. Noise on
the data lines will cause the settling time to be large. If the mismatch between a data line and the
associated strobe is too great, or there is noise on the interface, incorrect data will be sampled.
The low-voltage operation on AGP (1.5 V) requires even more noise immunity. For example, during
1.5-V operation, V
issues.
The Intel 855GME GMCH AGP interface supports a single AGP controller. LOCK# and
SERR#/PERR# are not supported. AGP 4X, 2X, and 1X operate at 1.5 V only.
AGP semantic cycles to DRAM are not snooped on the host bus.
The Intel 855GME GMCH supports PIPE# or SBA[7:0] AGP address mechanisms, but not both
simultaneously. Either the PIPE# or the SBA[7:0] mechanism must be selected during system
initialization.
The AGP interface is clocked from the 66-MHz clock input to the GCLKIN pin on the GMCH.
9.1.1.
AGP Interface Signal Groups
The signals on the AGP interface are broken into three groups: 1X timing domain signals, 2X timing,
and 4X timing domain signals. Each group has different routing requirements.
®
Intel
855GM/855GME Chipset Platform Design Guide
is 570 mV. Without proper isolation, crosstalk could create signal integrity
il max
AGP Port Design Guidelines
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