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6.4.1
PCI Clock Layout Guidelines
The PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, allows a maximum of
0.5 ns clock skew timing for each of the PCI-X frequencies: 66 MHz, 100 MHz and 133 MHz. A
typical PCI-X application may require separate clock point-to-point connections distributed to each
PCI device. 80331 provides four buffered clocks on the secondary PCI bus, S_CLKO[3:0]to
connect to multiple PCI-X devices. The
outputs and length matching requirements. The recommended clock buffer layout are specified as
follows:
•
Match each of the 80331 output clock lengths to within 25 mils to help minimize the skew.
•
Keep distance between clock lines and other signals "d" at least 25 mils from each other.
•
Keep distance between clock line and itself "a" at a minimum of 25 mils apart (for serpentine
clock layout).
•
S_CLKIN gets connected to S_CLKOUT through a 22 ohm resistor
•
The 22 ohm resistor is placed within 1" maximum distance of S_CLKOUT.
•
A series termination resistor with the value of 22 ohm resistor is placed within 1" maximum
distance of each of the clock outputs SCLKO[3:0].
Note: Using the value of 33.2 ohm for the series termination resistor is also acceptable.
Figure 16.
PCI Clock Distribution and Matching Requirements
Notes:
– PCI Clock lengths X0, X1, X2, X3 and X4 should be matched within 25 mils of each other.
– Minimum separation between two different CLKs, "d"
– Minimum separation between two segments of the same CLK line, "a"
– 22 Ohm resistor must be placed less than 1" of the S_CLKOUT output.
– 22 Ohm resistors must be placed less than 1" of the S_CLKO[0:3] outputs.
S_CLKIN
®
Intel
S_CLKO0
80331
S_CLKO1
I/O
Processor
S_CLKO2
S_CLKO3
S_CLKOUT
22
Intel® 80331 I/O Processor Design Guide
Figure 16
shows the use of four secondary PCI clock
22
X0
a
22
X1
d
X2
X4
22
X3
PCI-X Layout Guidelines
PCI
Device 1
PCI
Device 2
PCI
Device 3
PCI
Device 4
B1613-04
45
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