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Table 37.
DDR2 Signal Groups (Sheet 2 of 2)
Group
DC Bias (I/O)
9.5
Package Length Compensation
Package length compensation is required for total routing length requirements, see the
length matching rules listed in
®
the Intel
9.6
Length Matching and Length Formulas
The routing guidelines presented in the following subsections define the recommended
routing topologies, trace width, spacing geometries, and absolute minimum and
maximum routed lengths for each signal group. These guidelines are recommended to
achieve optimal signal integrity and timing.
Table 38.
Length Matching Formulas between EP80579 and DDR2 DIMM
Source/
Destination
EP80579 Pad to
DDR2 DIMM
Notes:
1.
Length matching is only required within each Byte lane. Signal length matching is not required
outside the Byte lane. For example, any signal within DQ [0:7] need not be length matched to DQS
[3].
2.
Total length means - L
9.7
DDR2 Interface System Interconnect
Figure 75
DDR2 Memory Controller and the two DIMMs for the signal groups provided in
The Command/Address and Control signals require external terminations. External
terminations are not required for DQ and DQS signals since both the EP80579 and the
SDRAMs contain internal ODT. The following sections provide the detailed topology and
routing guidelines for each of the signal groups.
®
Intel
EP80579 Integrated Processor Product Line
Platform Design Guide
119
®
Intel
EP80579 Integrated Processor Product Line—System Memory Interface (DIMM)
Signal Name
DDR_CRES[2:0]
DDR_SLWCRES
DDR_RCOMPX
DDV_CRES
DDR_VREF
Table
EP80579 Integrated Processor Product Line Datasheet for more information.
Signal Group to matching
signal
DQS to DQ/DM
DQS to clock
CMD/ADD to Clock
CTRL to CMD/ADD
Clock to Clock#
+ L
PKG
BREAK
provides a block diagram of the system interconnect between the EP80579
• DDR_CRES[2:1] - Impedance compensation resistors.
• DDR_CRES[0] - Common return for DDR2 interface
compensation resistors on DDV_CRES,
DDR_SLWCRES and DDR_RCOMPX
Slew rate compensation for DDR2 interface (Analog)
Impedance compensation for DDR2 interface
DDR2 resistor
Voltage Reference (Analog)
38. See the DDR2 Package length information in
Total Length Matching Tolerances
DQS = DQ/DM + 400 mils
DQS = CLK/CLK# ± 500 mils
CMD/ADD = CLK/CLK# ± 20 mils
CTRL = CMD/ADD + 2.5 inches
CLK[x] = CLK[x]# ±10 mils
+ L
ROUTE
Description
Comments
1,
2
2
2
2
2
Table
May 2010
Order Number: 320068-005US
37.
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