Figure 51. Control Signal To Clock Trace Length Matching Diagram - Intel 852GM Design Manual

System Memory Design Guidelines (DDR-SDRAM)

Figure 51. Control Signal to Clock Trace Length Matching Diagram

GMCH Package
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pads.
GMCH Package
Note: All lengths are measured from GMCH
die pad to SO-DIMM connector pads.
104
SCS#[1:0]
SCKE[1:0]
GMCH
Die
SCK[1:0]
SCK#[1:0]
SCS#[3:2]
SCKE[3:2]
GMCH
Die
SCK[4:3]
SCK#[4:3]
SO-DIMM0
CNTRL Length = Y0
(X0 – 1.0" ) <= Y0 <= (X0 + 0.5")
Clock Ref. Length = X0
SO-DIMM0 SO-DIMM1
(X1 – 1.0") <= Y1 <= (X1+ 0.5")
®
Intel 852GM Chipset Platform Design Guide
R
CNTRL Length = Y1
Clock Ref. Length = X1